SP65: 65nm Standard Cell ASIC

• Technology definition: 65 nm
• Up to 100 M logic gates and 180 M bits of SRAM
• Excellent performance:
  • 850 MHz for an 18 x 18 Multiplier
  • 0.8 ns delay for a 1 k x 32 DPRAM
  • 0.9, 1.0, 1.1, 1.2 V core operation
  • 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5 V tolerant I/O cells
• Power dissipation: 1.1 nW/MHz/gate (FO=0; V_DD=1.0 V)
• Junction temperature range: -40° C to 125° C
• Cost driven architecture:
  • Up to 9 levels of metal (including RDLs)
  • Wire-bond packaging for small to medium I/O count devices
  • Flip-chip packaging for larger I/O count devices or for high performance applications
• Standard cell library:
  • General purpose and low power technology
  • Multiple track sizes
  • Various supply voltage for voltage island
  • Several Vt options
• I/O cell options:
  • GPIO
  • Transceiver: PCI, I²C, LVDS, SSTL, HSTL, PECL, MII, CML
  • Tall, short, in-line, staggered, area I/O
• Memory support:
  • Synchronous single port, dual port, register file, ROM
  • OTP and e-fuse
  • SRAM repair feature for high yield
  • In-system memory BIST
  • Optional flash and DRAM
• Memory interface:
  • DDR1, 2 and 3 interface
  • mDDR interface
  • SD card interface
  • PCMCIA
• Communication interface
  • PCIe Gen1, 2 and 3
  • XAUI, SATA
  • USB1, 2 and 3
  • MIPI M-PHY and D-PHY
  • HDMI 1.3 and 1.4

• ARM processor family
  • ARM Classic (7,9,11), M Series, A Series, R Series
  • APB, AHB, AXI interface
  • Other processor
• Analog cell
  • Data converter (ADC, DAC)
  • Amplifier
  • Comparator
  • Power management (Regulator)
  • Timing block(PLL)
• Low power
  • Integrated gated clock
  • Multi Vt optimization
  • Voltage island
  • Power gate leakage reduction
• Extensive packaging capabilities:
  • 0.5 mm to 1.27 mm pitch BGAs
  • CSPs, QFPs, QFNs, TQFPs, PLCCs, LCCs, JLCCs
  • Stacked packages with flash, DRAM
  • Burn-in capability as required
• FPGA conversion specific memory features:
  • Output register mode, shift register mode, FIFO mode
  • Xilinx read before write and no change mode
  • Altera MRAM size
• Extensive DFT methodology:
  • At speed DFT implementation
  • In-system memory BIST and logic BIST
  • IEEE1149* standard
  • DFM and DFQ targeted DFT approach
• ESD protection 2,000 V HBM, 500 V CDM, 200 V MM
• Latchup >200 mA @ 125° C
• MLR (Multi Layer Reticles) available

SP65 targets low to high volume digital ASIC products in the Military and Aerospace, Industrial, Networking & Telecommunications, Computing and Consumer markets. The high performance capabilities of the process make SP65 ideal for high speed applications, including high performance ARM processor, Memory interface, Communication interface and Analog cells. Combined with support for a rich family of IP, SP65 supports applications in military munitions, radar systems, avionics, secure communications, wireless infrastructure, industrial controls, printers and infotainment. The ON Semiconductor RTL signoff, netlist hand-off and optional Spec handoff flows provide quick and seamless access for SP65 designs.

Targeted Quality Standards
SP65 offers manufacturing options that includes ITAR and DO-254 support and meets the specific quality standards needed to support military and aerospace applications.

Second Source for Existing Products
The ASIC-to-ASIC conversion capability from ON Semiconductor allows SP65 to be a cost-effective alternative supply for existing high-volume products.

FPGA Prototype Designs
Based on the extensive experience of ON Semiconductor with FPGA conversions, ASIC designs prototyped in FPGAs, or those which are partially prototyped or partitioned between FPGAs and other devices such as DDR, SerDes, or USB interfaces can be integrated into a single SP65 device.

ON Semiconductor can also provide customers with a comprehensive library of soft IP that can be prototyped in an FPGA, further easing the process of getting to a cost competitive, low power ASIC for production.

FPGA Conversion
The SP65 product roadmap will be expanded to offer support for 0.9~1.2 V FPGA devices, including:

• Full I/O
• Memory feature compatibility
• DLL/PLL equivalence
• System IP enablement