SC5

SC5: 0.5 µm CMOS Standard Cell

The onsemi SC5 standard cell family combines compact, building block standard cells and soft IP with high speed memory and datapath functions. Using a 0.5 μm, high performance CMOS process, the SC5 family offers support for legacy 5 V applications and is a lower cost alternative to gate arrays for high volume applications.

Parameters

Feature

Up to 1.6 M logic gates and 1.6 M bits of RAM

Operating temperature range -55 to 150°C

JTAG boundary scan macro support

Full operating voltage range from 2.25 V to 5.5 V

ESD protection > 2 kV; Latchup > 100 mA

High speed operation, power dissipation: 2.95 μW/MHz/gate (FO=1; VDD=5.0 V)

Low power operation, power dissipation: 0.62 μW/MHz/gate (FO=1; VDD=3.3 V)

Ultra-low power operation, power dissipation: 0.20 µW/MHz/gate (FO=1; VDD=2.5 V)

Feature

Parameters

Excellent performance

496 MHz maximum toggle rate on clocked flip-flops
High speed operation: 103 ps delay for a 2-input NAND gate (FO=2; L=0 mm)
Low power operation: 128 ps delay for a 2-input NAND gate (FO=2; L=0 mm)
6ns clock-to-out performance (CL = 35 pF)

Mixed voltage operation

Split power supply bussing between core and pads
5.0 V, 3.3 V or 2.5 V core operation
5.0 V and 3.3 V I/O pads
5 V tolerant I/O cells

Cost driven architecture

2 or 3 level metal interconnect provides lowest device cost for gates and pads required

Extensive library for quick design

Complete core cell and I/O library
IP functions include processors, peripherals and datapath synthesizers

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Applications

SC5 standard cell technology targets legacy 5 V applications and high volume digital ASIC products. The low device cost accommodates designs requiring significant on-board memory, data path logic or IP blocks.

SC5 wafers are produced in onsemi's domestic wafer fab. In addition onsemi offers a complete on-shore flow including design, mask generation, silicon, packaging, and test complete with ITAR and NOFORN processing to support government and military programs. SC5 has extensive flight heritage.

Mid-Range ASIC Design

SC5 provides a cost effective solution for mid-range applications with gate counts up to 1.6 million gates and up to 1.6 million bits of memory. Combined with support for a rich family of I/O standards, the onsemi RTL sign-off and netlist hand-off flows provide quick and seamless access for SC5 designs.

FPGA Conversion

SC5 provides an ideal platform to cost reduce or replace obsolete 5 V PLD and FPGA devices, or even advanced FPGAs with suitable performance requirements. SC5 provides extensive support for FPGA memory and timing generator features, including live at power up (LAPU capability).

Support for EOL Products

onsemi's FPGA-to-ASIC and ASIC-to-ASIC conversion capabilities allow SC5 to be a cost-effective, long-term solution for 5 V end-of-life products.

Process Upgrade

onsemi ASICs designed in 1.25 μm, 1.0 μm, 0.8 μm, 0.6 μm processes, and any legacy 5 V core technology can be easily upgraded to the SC5 family. The onsemi ASIC library provides a common netlist design base.

Adding Custom Blocks

onsemi specializes in combining digital and analog functions in custom ASICs. Analog functions include ADCs and DACs, op-amps and comparators, EMI/RFI filters, AC-DC and DC-DC controllers and regulators, drivers, thermal management, voltage and current management, and digital potentiometers.

Design Flow

onsemi ASICs are supported on leading third-party software platforms:

Mentor Graphics™

Synopsys®

Cadence®

The onsemi design flow integrates leading third-party design tools with ON Semiconductor proprietary tools to offer a flexible design interface for mid-range ASIC designs with RTL sign-off, ASIC netlists for ASIC-to-ASIC conversion and FPGA designs for FPGA-to-ASIC conversion. The ON Semiconductor software support methodology ensures a tight, well-coupled flow from design to production. The dedicated, experienced engineering staff from ON Semiconductor can assist at any step of the design process.