SC3: 0.35 µm CMOS Standard Cell
The ON Semiconductor SC3 standard cell family combines compact, building block standard cells and soft IP with high speed memory and datapath functions. Using a 0.35 μm, high performance CMOS process, the SC3 family offers a lower cost alternative to gate arrays for high volume applications.
SC3 standard cell technology targets high volume digital ASIC products. The low device cost accommodates designs requiring significant on-board memory, data path logic or IP blocks.
SC3 wafers are produced in ON Semiconductor's domestic wafer fab. In addition ON Semiconductor offers a complete on-shore flow including design, mask generation, silicon, packaging, and test complete with ITAR and NOFORN processing to support government and military programs. SC3 has extensive flight heritage.
Mid-Range ASIC Design: SC3 provides a cost effective solution for mid-range applications with gate counts up to 2 million gates and up to 2 million bits of memory. Combined with support for a rich family of I/O standards, the ON Semiconductor RTL sign-off and netlist hand-off flows provide quick and seamless access for SC3 designs.
ON Semiconductor ASICs are supported on leading third-party software platforms:
- Mentor Graphics™
The ON Semiconductor design flow integrates leading third-party design tools with ON Semiconductor proprietary tools to offer a flexible design interface for mid-range ASIC designs with RTL sign-off, ASIC netlists for ASIC-to-ASIC conversion and FPGA designs for FPGA-to-ASIC conversion. The ON Semiconductor software support methodology ensures a tight, well-coupled flow from design to production. The dedicated, experienced engineering staff from ON Semiconductor can assist at any step of the design process.