feedback
Rate this webpage
Need
Support?


I3T80: 0.35 µm Process Technology

Providing the density of a 0.35 µm digital process, analog/mixed-signal capability and high voltage, the ON Semiconductor Intelligent Interface Technology I3T80 process is the answer to the need for increased digital content in a mixed-signal and/or high voltage environment. Featuring high voltage devices up to 80 V as well as digital and analog operation at 3.3 V, the I3T80 process family features a wide range of capabilities in a single IC.


Features

  • 3 to 5 metal layers
  • Metal to metal (MIM) linear capacitors
  • High, medium, and low resistivity polysilicon resistors
  • Floating high-voltage NDMOS and PDMOS transistors
  • Floating medium-voltage NDMOS
  • Floating high- and low-voltage diodes
  • Medium-voltage NPN bipolar transistors
  • Medium-voltage PNP bipolar transistors (collector grounded, high and low gain)
  • Zener zap diode for OTP• Buried zener diode for clamping
  • Polysilicon clamping diode
  • High- and medium-voltage floating metal capacitors
  • Deep n+ doped guard rings

Process Characteristics

Parameter Value
Operating Voltage 3.3 V
Substrate Material N-epitaxy on P-sub, retrograde wells
Drawn Transistor Length 0.35 µm
Gate Oxide Thickness 7.0 nm
Contact/Via Size 0.4 µm
Contacted Gate Pitch 1.3 µm
Top Metal Thickness 1020 nm

Process Characteristics - Contacted Metal Pitch

Parameter Value
Metal 1/CNT 1.1 µm
Metal 1/Via 1 1.2 µm
Metal 2 to Top 1/Via 1.2 µm
Metal Composition Al/Cu
Isolation LOCOS
ILD Planarization USG/BPTEOS+CMP
IMD Planarization HDP/PETEOS+CMP

Metal Pitch

Parameter Value
Metal 1 1.0 µm
Metal 2 1.1 µm
Top Metal 1.4 µm

Sample Process Options

Parameter Mask Layers
3 metal, 80 V, MIMC, HIPO, OTP 23
4 metal, 80 V, MIMC, HIPO, OTP 25
4 metal, 80 V, MIMC, HIPO, OTP, Flash EEPROM 28

Device Characteristics

(All Values Typical at 25°C)

Low-Voltage Transistors

NMOS Transistor Typical Value Unit PMOS Transistor Typical Value Unit
Vt (10/0.35, linear extrapolated) 0.59 V Vt (10/0.35, linear extrapolated) -0.57 V
Vmax=Vbd 3.6 V Vmax=Vbd -3.6 V
IDS (10/0.35, Vds=Vgs=3.3 V) 530 µA/µm IDS (10/0.35, Vds=Vgs=3.3 V) -250 µA/µm

Bipolar Transistors

Vertical Medium-Voltage PNP: VPB (Parameter, E_area=0.64µm²) Typical Value Unit
Hfe @ Ic=10 µA 8 -
Bvceo @ Ic=1 µA -63 V
Bvces @ Ic=1 µA -67 V
Icmax 250 µA
Vertical Medium-Voltage “High Gain” PNP Transistor: VPHB (Parameter, E_area=0.64µm²) Typical Value Unit
Hfe @ Ic=100 nA 115 -
Bvceo @ Ic=1 µA >80 V
Bvces @ Ic=1 µA >100 V
Icmax 250 µA
Medium Voltage NPN (Parameter, E_area=16 µm²) Typical Value Unit
Hfe max 120 -
Bvceo @ Ic=1 µA 23 V
Bvces @ Ic=1 µA >80 V
Icmax >70 V

High-Voltage Transistors

Floating NMOS @ 80 V Typical Value Unit Floating PMOS @ 80 V Typical Value Unit
Vt (10/0.35, linear extrapolated) 0.59 V Vt (10/0.35, linear extrapolated) -0.57 V
Vmax=Vfloat to P-substrate 80 V Vmax=Vfloat to P-substrate 80 V
Vmax=Vbd 3.6 V Vmax=Vbd -3.6 V
IDS (10/0.35, Vds=Vgs=3.3 V) 530 µA/µm IDS (10/0.35, Vds=Vgs=3.3 V) -250 µA/µm
Floating NDMOS for Switching Application: VFNDM80 Typical Value Unit Floating NDMOS for Analog Application: VFNDM80A Typical Value Unit
Vt 0.54 V Vt 0.56 V
Vmax=Vbd (higher if self protected) 70 V Vmax=Vbd (higher if self protected) 70 V
Vgsmax (full lifetime) 3.6 V Vgsmax (full lifetime) 3.6 V
Ids (Vds=40, Vgs=1.5 V) 100 µA/µm Ids (Vds=40, Vgs=1.5 V) 70 µA/µm
Ron*Area (block of 16 fingers) Ron*Area (block of 16 fingers)
Without isolation 180 mΩ*mm² Without isolation 250 mΩ*mm²
With isolation 260 mΩ*mm² With isolation 325 mΩ*mm²
Floating Medium Voltage NDMOS Typical Value Unit Floating HV PMOS: LFPDM80 Typical Value Unit Floating PDMOS: LFPDMS Typical Value Unit
Vt 0.58 V Vt -0.56 V Vt -0.56 V
Vmax=Vbd 14 V Vmax=Vbd -70 V Vmax=Vbd -5.5 V
Vgsmax (full lifetime) 3.6 V Vgsmax (full lifetime) -3.6 V Vgsmax -3.6 V
Ids (Vds=10 V, Vgs=+3.3 V) 300 µA/µm Ids (Vds=-40V, Vgs=-1.5 V) 18.5 µA/µm Ids (Vds=-5 V, Vgs=-3.3 V) 96 µA/µm
Ron*Area 31 mΩ*mm² Ron*Area 280 mΩ*mm²

Diodes

Zener Diode: PBZD (a=2µm) Typical Value Unit Zapping Zener Diode for OTP: UZZD Typical Value Unit
Vz @ 100 µA 4.6 V Vz @ 1 A 1.5 V
Rzener 45 Ω Vbd @ 10 mA 4.5 V
Ileak @ Vz=0.5 V 200 nA Ileak_max @ Vz= 1 V 1.4 mA
Floating High Voltage Diode: FID80 Typical Value Unit Poly Diode for Gate Clamping: POLYD Typical Value Unit
Vak_reverse, la=-100 nA >80 V Vreverse @ Ia=10 µA 6.8 V
Vak_forw, lk=100 µA 0.79 V Ileak/W @ Vrev=3.6 V <20< /td> nA/µm
Isub/IA, Va=0.7 V 0.5 %

Capacitors (Parameter @ 25°C)

Type (Maximum Voltage) Typical Value Unit
Metal2/Metal2.5 Plate: MIMC (3.6 V) 1.5 fF/µm²
Metal1/Metal3 Plate (80 V) 0.1 fF/µm²
Poly/Metal3 Plate (80 V) 0.14 fF/µm²
Metal1/Metal3 Bar (80 V) 0.26 Ω/square
Poly/Metal3 Bar (80 V) 0.33 Ω/square

Resistors

Resistor Type Typical Value Unit
High-Resistance Poly: HIPO 1.5 Ω/square
Salicided P+ Poly: LOPOR 0.1 Ω/square
Unsalicided P+ Poly: PPOLR 0.14 Ω/square
Unsalicided P+ in Mwell 0.26 Ω/square
Unsalicided N+ Poly: NPOLR 0.33 Ω/square
Unsalicided N+ in Pwell 0.26 Ω/square
Nwell under FOX (field oxide) 0.33 Ω/square
Nwell in AA (active area) 0.26 Ω/square
Pwell in AA (active area) 0.33 Ω/square

Libraries

Standard Cell - Ultra High Density Core Cell
pn sum: 2.0
Area of 2-input nand (na21): 38.88 µm
Gate density (na21 @ 100% utilization): 25.72 k gates/mm²
Scan Flop density (scan flops @100% utilization): 3.215 k ff/mm²
Average power (@ 3.3 V): 0.2929 µW/MHz/gate
Standard I/O - Fat Pad I/O Library (for core limited designs) Tall Pad I/O Library (for pad limited designs)
190.80 µm min in-line pad pitch 203.40 µm pad height
97.20 µm min in-line pad pitch 374.40 µm pad height

Memory Options

RAM

Synchronous High Speed/High Temp Single Port SRAM Synchronous High Speed/High Temp Dual Port SRAM Low Power Synchronous SRAM
Minimum: 16 words x 2 bits Minimum: 16 words x 2 bits Minimum: 64 words x 4 bits
Maximum: 128 k bits (ie: 16 k words x 8 bits, 8 k words x 16 bits, …) Maximum: 128 k bits (ie: 16 k words x 8 bits, 8 k words x 16 bits, …) Maximum: 128 k bits (ie: 16 k words x 8 bits, 8 k words x 16 bits, …)

ROM

Synchronous High Speed/High Temp Diffusion ROM Low Power Synchronous Via Programmable ROM
Minimum: 256 words x 4 bits Minimum: 256 words x 4 bits
Maximum: 512 k bits (ie: 64 k words x 8 bits, 32 k words x 16 bits, …) Maximum: 512 k bits (ie: 64 k words x 8 bits, 32 k words x 16 bits, …)

Non-Volatile Memory

OTP – One Time Programmable
Fuse: Zener Diode optimized for low power zapping
Both Serial and Parallel Output Capability
In field programming available
Vector: Up to 320 bits

CAD Tool Compatibility

Digital Design
Synopsys Design Compiler
Cadence Verilog
Analog Design
Cadence DFII (4.4.6)
Spectre
Place and Route
Synopsys Apollo
Cadence Silicon Ensemble
Physical Verification
Mentor Calibre

For more information please contact your local sales support.

Your request has been submitted for approval.
Please allow 2-5 business days for a response.
You will receive an email when your request is approved.
Request for this document already exists and is waiting for approval.