MOSFETs | FDC6302P

Dual P-Channel Digital FET -25V, -0.12A, 10Ω

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Overview

These Dual P-Channel logic level enhancement mode field effect transistors are produced using a proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors in load switchimg applications. Since bias resistors are not required this one P-Channel FET can replace several digital transistors with different bias resistors like the IMBxA series.

  • This product is general usage and suitable for many different applications.
  • -25 V, -0.12 A continuous, -0.5 A Peak
  • RDS(ON) = 13 Ω @ VGS= -2.7 V
  • RDS(ON) = 10 Ω @ VGS = -4.5 V
  • Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5V
  • Gate-Source Zener for ESD ruggedness. >6kV Human Body Model
  • Replace multiple PNP digital transistors (IMHxA series) with one DMOS FET

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Status

CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

Channel Polarity

Configuration

V(BR)DSS Min (V)

VGS Max (V)

VGS(th) Max (V)

ID Max (A)

PD Max (W)

RDS(on) Max @ VGS = 2.5 V (mΩ)

RDS(on) Max @ VGS = 4.5 V (mΩ)

RDS(on) Max @ VGS = 10 V (mΩ)

Qg Typ @ VGS = 4.5 V (nC)

Qg Typ @ VGS = 10 V (nC)

Ciss Typ (pF)

Pricing ($/Unit)

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FDC6302P

Obsolete

Pb

A

H

P

TSOT-23-6

419BL

1

260

REEL

3000

N

P-Channel

Dual

-25

-8

-1.5

-0.12

0.9

Q1=Q2=13000

10000

-

1.1

0.22

11

Price N/A

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