ONC18: 0.18 µm CMOS Standard Cell

The ONC18 standard cell family combines high performance and low power core libraries and memory with extensive I/O capabilities and advanced off-chip memory interfaces. Using a high performance 0.18 µm CMOS process, the ONC18 family offers small die sizes for low cost, medium to high volume applications.

Parameters

Feature

Up to 10 M logic gates and 7 M bits of RAM

Junction temperature range -55°C to 150°C

PLL timing generators

Latchup >100 mA @ 85°C

MLR (Multi Level Reticles) available

Feature

Parameters

Process technology

  • 0.18 µm ONC18 High Performance (HP) process
  • Up to 6 layers of metal and RDL

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Excellent power & performance

  • 4 ns for a zero stage pipelined 18x18 multiplier at 125°C
  • High speed - 266 MHz local clock performance
  • 1.8 V or 1.5 V core operation
  • 1.5 V,1.8 V, 2.5 V, 3.3 V I/O cells
  • 3.3 V/5 V tolerant I/O cells
  • High Threshold Voltage (HVt) logic and memories available for designs requiring low leakage

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Optimal combination of density, speed, performance and price

  • High density : 125,000 gates / mm2
  • Low power : 46 nW/MHz/gate (FO=1; VDD=1.8 V )

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Wide variety of soft and hard IP

  • 10/100 ethernet MAC, I²C
  • R8051, ARM cores & peripherals
  • DDR and DDR2 byte lane plus controllers

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Extensive memory support

  • Synchronous single and dual port up to 16 K x 64
  • Dedicated BIST ports
  • Memory compilers optimized for speed, density, and low power
  • Memory performance to 360 MHz for a 2048 x 32 Single Port SRAM configuration
  • Programmable ROM available

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FPGA conversion specific memory feature

  • Output register mode, shift register mode, FIFO mode
  • Xilinx read before write
  • Xilinx no change mode
  • Altera MRAM size

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Extensive I/O cell options

  • LVTTL, LVCMOS, PCI 33/66, SSTL I/II, HSTL, LVPECL , LVDS, DCI
  • 25 Ω or 50 Ω output impedance for Digitally Controlled Impedance

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Extensive packaging capabilities

  • 0.65 mm to 1.27 mm pitch BGAs
  • CSPs, QFPs, CQFPs, TQFPs, PLCCs, LCCs, JLCCs
  • Differential pair matching
  • Controlled impedance traces
  • Stacked packages with flash
  • Burn-in capability as required

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Extensive DFT methodology

  • Scan-chain insertion and reordering
  • Built-in self test (BIST) for memory blocks
  • Automatic test program generation (ATPG)
  • JTAG boundary scan insertion

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ESD protection meets or exceeds JEDEC standards

  • 2,000 V HBM
  • 500 V CDM
  • 250 V MM

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Applications

ONC18 wafers are produced in onsemi's domestic wafer fab. In addition onsemi offers a complete on-shore flow including design, mask generation, silicon, packaging, and test complete with ITAR and NOFORN processing to support government and military programs. As a result, ONC18 is a perfect fit for military and commercial avionics, military munitions and radar systems. Other application focuses include industrial applications, commercial and military communications including wireless infrastructure and other end applications.

The small die size and low device cost accommodates designs requiring significant on-board memory and logic. The high performance capabilities of the process make ONC18 ideal for many applications, including those requiring 10/100 Ethernet MAC, CAN 2.0 and I2C.

Low power core libraries and memories allow ONC18 to meet power-sensitive ASIC requirements. Coupled with onsemi's on-shore capabilities, ONC18 is a strong solution for battery powered and secure applications in a wide range of harsh environments. ONC18 provides a cost effective solution for mid-range applications with gate counts up to 10 million and up to 7 million bits of memory. Combined with support for a rich family of I/O standards, the onsemi RTL sign-off and netlist hand-off flows provide quick and seamless access for ONC18 designs.

Application
Second Source for Existing Products

The ASIC-to-ASIC conversion capability from onsemi allows ONC18 to be a cost-effective alternative supply for existing high, medium and even low-volume products.

Application
FPGA Prototype Designs

Based on the extensive experience of onsemi with FPGA conversions, ASIC designs prototyped in FPGAs, or those which are partially prototyped or partitioned between FPGAs and other devices, can be integrated into a single ONC18 device.

Application
FPGA Conversion

The ONC18 product roadmap will be expanded to offer full support for 1.8 V and 1.5 V FPGA devices, including full I/O and memory feature compatibility and DLL/PLL equivalence.

Application
Adding Custom Blocks

onsemi specializes in combining digital and analog functions in custom ASICs. Analog functions include ADCs and DACs, op-amps and comparators, EMI/RFI filters, AC-DC and DC-DC controllers and regulators, drivers, thermal management, voltage and current management, and digital potentiometers.

Design Flow

onsemi ASICs are supported on leading third-party software platforms:

Software
Mentor Graphics™
Software
Synopsys®
Software
Cadence®

The onsemi design flow integrates leading third-party design tools with ON Semiconductor proprietary tools to offer a flexible design interface for mid-range ASIC designs with RTL sign-off, ASIC netlists for ASIC-to-ASIC conversion and FPGA designs for FPGA-to-ASIC conversion. The ON Semiconductor software support methodology ensures a tight, well-coupled flow from design to production. The dedicated, experienced engineering staff from ON Semiconductor can assist at any step of the design process.

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