ONC18: 0.18 µm CMOS Standard Cell
The ONC18 standard cell family combines high performance and low power core libraries and memory with extensive I/O capabilities and advanced off-chip memory interfaces. Using a high performance 0.18 µm CMOS process, the ONC18 family offers small die sizes for low cost, medium to high volume applications.
ONC18 wafers are produced in ON Semiconductor's domestic wafer fab. In addition ON Semiconductor offers a complete on-shore flow including design, mask generation, silicon, packaging, and test complete with ITAR and NOFORN processing to support government and military programs. As a result, ONC18 is a perfect fit for military and commercial avionics, military munitions and radar systems. Other application focuses include industrial applications, commercial and military communications including wireless infrastructure and other end applications.
Low power core libraries and memories allow ONC18 to meet power-sensitive ASIC requirements. Coupled with ON Semiconductor's on-shore capabilities, ONC18 is a strong solution for battery powered and secure applications in a wide range of harsh environments. ONC18 provides a cost effective solution for mid-range applications with gate counts up to 10 million and up to 7 million bits of memory. Combined with support for a rich family of I/O standards, the ON Semiconductor RTL sign-off and netlist hand-off flows provide quick and seamless access for ONC18 designs.
ON Semiconductor ASICs are supported on leading third-party software platforms:
- Mentor Graphics™
The ON Semiconductor design flow integrates leading third-party design tools with ON Semiconductor proprietary tools to offer a flexible design interface for mid-range ASIC designs with RTL sign-off, ASIC netlists for ASIC-to-ASIC conversion and FPGA designs for FPGA-to-ASIC conversion. The ON Semiconductor software support methodology ensures a tight, well-coupled flow from design to production. The dedicated, experienced engineering staff from ON Semiconductor can assist at any step of the design process.