P-Channel Logic Level Enhancement Mode Field Effect Transistor -20V, -24A, 50mΩ

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Overview

These logic level P-Channel enhancement mode power field effect transistors are produced using ON Semiconductor's proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as automotive, DC/DC converters, PWM motor controls, and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.

  • This product is general usage and suitable for many different applications.
  • -24 A, -20 V
    RDS(ON) = 0.05 Ω @ VGS= -4.5 V
    RDS(ON) = 0.07 Ω @ VGS= -2.7 V
    RDS(ON) = 0.075 Ω @ VGS= -2.5 V.
  • Critical DC electrical parameters specified at elevated temperature.
  • Rugged internal source-drain diode can eliminate the need for an external Zener diode transient suppressor.
  • 175°C maximum junction temperature rating.
  • High density cell design for extremely low RDS(ON).
  • TO-220 and TO-263 (D2PAK) package for both through hole and surface mount applications.

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ECAD Models

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MSL Temp (°C)

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Channel Polarity

Configuration

V(BR)DSS Min (V)

VGS Max (V)

VGS(th) Max (V)

ID Max (A)

PD Max (W)

RDS(on) Max @ VGS = 2.5 V (mΩ)

RDS(on) Max @ VGS = 4.5 V (mΩ)

RDS(on) Max @ VGS = 10 V (mΩ)

Qg Typ @ VGS = 4.5 V (nC)

Qg Typ @ VGS = 10 V (nC)

Ciss Typ (pF)

Pricing ($/Unit)

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NDP6020P

Obsolete

Pb

A

H

P

TO-220-3

NA

0

TUBE

800

N

P-Channel

Single

-20

8

-1

-24

60

75

50

50

-

25

1590

Price N/A

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