Dual N & P Channel Digital FET 25V

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Overview

These dual N & P-Channel logic level enhancement mode field effect transistors are produced using a proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values.

  • This product is general usage and suitable for many different applications.
  • N-Ch 0.22 A, 25 V,
    RDS(ON) = 4.0 Ω @ VGS= 4.5 V,
    RDS(ON) = 5.0 Ω @ VGS= 2.7 V.
  • P-Ch -0.14 A, -25 V,
    RDS(ON) = 10 Ω @ VGS= -4.5 V,
    RDS(ON) = 13 Ω @ VGS= -2.7 V.
  • Very small package outline SC70-6.
  • Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V).
  • Gate-Source Zener for ESD ruggedness (>6kV Human Body Model).

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Product

Status

CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

V(BR)DSS Min (V)

RDS(on) Max @ VGS = 10 V (mΩ)

Channel Polarity

Configuration

VGS Max (V)

VGS(th) Max (V)

ID Max (A)

PD Max (W)

RDS(on) Max @ VGS = 2.5 V (mΩ)

RDS(on) Max @ VGS = 4.5 V (mΩ)

Qg Typ @ VGS = 4.5 V (nC)

Qg Typ @ VGS = 10 V (nC)

Ciss Typ (pF)

Reference Price

FDG6320C

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Last Shipments

CAD Model

Pb

A

H

P

SC-88-6 / SC-70-6 / SOT-363-6

1

260

REEL

3000

N

±25

-

Complementary

Dual

-8

±1.5

N: 0.22, P: -0.14

0.3

N:5000, P:13000

N: 4000, P:10000

-

0.22

12

Price N/A

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