NB3H63143G: 3.3 V / 2.5 V One Time Programmable OmniClock Generator with Single-Ended (LVCMOS/LVTTL) and Differential (LVPECL/LVDS/HCSL/CML) Outputs with Individual Output Enable and Individual VDDO
The NB3H63143G, which is a member of the OmniClock family, is a one−time programmable (OTP), low power PLL−based clock generator that supports any output frequency from 8 kHz to 200 MHz. The device accepts fundamental mode parallel resonant crystal or a single ended (LVCMOS/LVTTL) reference clock
as input. It generates either three single ended (LVCMOS/LVTTL)
outputs, or one single ended output and one differential
(LVPECL/LVDS/HCSL/CML) output. The output signals can be
modulated using the spread spectrum feature of the PLL
(programmable spread spectrum type, deviation and rate) for
applications demanding low electro−magnetic interference (EMI).
Individual output enable pins OE[2:0] are available to enable/disable
the outputs. Individual output voltage pins VDDO[2:0] are available
to independently set the output voltage of each output. Up to four
different configurations can be written into the device memory. Two
selection pins (SEL[1:0]) allow the user to select the configuration to
use. Using the PLL bypass mode, it is possible to get a copy of the
input clock on any or all of the outputs. The device can be powered
down using the Power Down pin (PD#). It is possible to program the
internal input crystal load capacitance and the output drive current
provided by the device. The device also has automatic gain control
(crystal power limiting) circuitry which avoids the device overdriving
the external crystal.
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Technical Documentation & Design Resources
Software (1) | Package Drawings (1) |
Application Notes (2) | Videos (5) |
Simulation Models (1) | Evaluation Board Documents (3) |
Data Sheets (1) |
Evaluation/Development Tool Information
Product | Status | Compliance | Short Description | Action | |
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NB3X6X1XXG16QFNEVK | Active |
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8 kHz to 200 MHz One Time Programmable Clock Generator Evaluation Kit for 16 lead QFN Package |
Availability & Samples
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Specifications
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Intaractive Block Diagram
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Case Outline |
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NB3H63143G00MNR2G | Active |
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NB3H63143G | QFN-16 | 485AE | 1 | 260 | Tape and Reel | 3000 | Contact Sales Office |
Market Leadtime (weeks) | : | Contact Factory |
Product
Description
Pricing ($/Unit)
Compliance
Status
Input Level
Output Level
VS Typ (V)
fin Typ (MHz)
fout Typ (MHz)
tJitter(Cy-Cy) Typ (ps)
tJitter(Period) Typ (ps)
tJitter(Φ) Typ (ps)
tR & tF Typ (ps)
tR & tF Max (ps)
TA Min (°C)
TA Max (°C)
Package Type
NB3H63143G00MNR2G
Pb
A
H
P
Active
Crystal
LVCMOS
CML
HCSL
LVCMOS
LVDS
LVPECL
2.5
3.3
3 to 200 (Reference clock)
3 to 50 (Crystal)
0.008 to 200
100
100
1000
700
-40
85
QFN-16
Case Outlines
485AE
Application
Diagram - Block
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