NB7L86M: 2.5 V / 3.3 V, 12 Gb/s Differential Clock / Data Smart Gate with CML Output and Internal Termination

Overview
Specifications
Datasheet: 2.5 V / 3.3 V 12 Gb/s Differential Clock/Data Smart Gate (2:1 Mux, AND/NAND, OR/NOR, XOR/XNOR) w/CML Output and Internal Termination
Rev. 7 (1416.0kB)
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»Product Change Notification (4)
Product Overview
Product Description
The NB7L86M is a multi-function differential Logic Gate, which
can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1
MUX. This device is part of the GigaComm family of high
performance Silicon Germanium products. The NB7L86M is an
ultra-low jitter multi-logic gate with a maximum data rate of 12 Gb/s
and input clock frequency of 8 GHz suitable for Data Communication
Systems, Telecom Systems, Fiber Channel, and GigE applications.

The device is housed in a low profile 3x3 mm 16-pin QFN package.

Differential inputs incorporate internal 50 Ω termination resistors
and accept LVNECL (Negative ECL), LVPECL (Positive ECL),
LVCMOS, LVTTL, CML, or LVDS. The differential 16 mA CML
output provides matching internal 50 Ω termination, and 400 mV
output swing when externally terminated 50 Ω to VCC.
Application notes, models, and support documentation are available
on www.onsemi.com.
Features
 
  • Maximum Input Clock Frequency up to 8 GHz
  • Maximum Input Data Rate up to 12 Gb/s Typical
  • 30 ps Typical Rise and Fall Times
  • 90 ps Typical Propagation Delay
  • 2 ps Typical Within Device Skew
  • CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
  • CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
  • CML Output Level (400 mV Peak-to-Peak Output) Differential Output
  • 50 Ω Internal Input and Output Termination Resistors
  • Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP and SG Devices
  • Pb-Free Packages are Available
Applications
  • Data routing in Data Communication Systems, Telecom Systems, Fiber Channel, and GigE applications.
  • Clock multiplexing for redundancy
Technical Documentation & Design Resources
Application Notes (14) Data Sheets (1)
Simulation Models (1) Package Drawings (1)
Availability and Samples
Product
Status
Compliance
Description
Package
MSL*
Container
Budgetary Price/Unit
Type
Case Outline
Type
Qty.
NB7L86MMNG Active
Pb-free
Halide free
2.5 V / 3.3 V, 12 Gb/s Differential Clock / Data Smart Gate with CML Output and Internal Termination QFN-16 485G-01 1 Tube 123 Contact Sales Office
NB7L86MMNR2G Active
Pb-free
Halide free
2.5 V / 3.3 V, 12 Gb/s Differential Clock / Data Smart Gate with CML Output and Internal Termination QFN-16 485G-01 1 Tape and Reel 3000 Contact Sales Office
Moisture Sensitivity level (MSL) for surface mount devices (lead free measured at 260°C reflow, non lead free at 235°C reflow)
Market Leadtime (weeks) :
Digi-Key   (2014-04-24 00:00) : <1K
Future Electronics   (2014-04-24 00:00) : <1K
Mouser   (2014-04-24 00:00) : <100
Market Leadtime (weeks) :
Datasheet: 2.5 V / 3.3 V 12 Gb/s Differential Clock/Data Smart Gate (2:1 Mux, AND/NAND, OR/NOR, XOR/XNOR) w/CML Output and Internal Termination
Rev. 7 (1416.0kB)
»View Reliability Data
»View Material Composition
»Product Change Notification (4)
Product Overview

Product Compliance Status Description Type Channels Input Level Output Level VCC Typ (V) fToggle Max (MHz) tpd Typ (ns) tJitter Typ (ps) tR & tF Max (ps) Package Type
 Pb-free 
 Halide free 
 Active     2.5 V / 3.3 V, 12 Gb/s Differential Clock / Data Smart Gate with CML Output and Internal Termination   SmartGate   1 
 CML 
 CMOS 
 ECL 
 LVDS 
 TTL 
 CML 
 2.5 
 3.3 
 8000   0.09   0.2   60   QFN-16 
 Pb-free 
 Halide free 
 Active     2.5 V / 3.3 V, 12 Gb/s Differential Clock / Data Smart Gate with CML Output and Internal Termination   SmartGate   1 
 CML 
 CMOS 
 ECL 
 LVDS 
 TTL 
 CML 
 2.5 
 3.3 
 8000   0.09   0.2   60   QFN-16 
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