Previously, in part one of our Fast Switches and Disruptive Simulation Ecosystems blog series we discussed ON Semiconductor’s Wide Band Gap unique ecosystem as well as the overview of our physical scalable models. In part two of our blog series, we will introduce some aspects of our silicon carbide power MOSFET model.
Now to introduce a few of the elements of the model shown below. First, let us discuss the key channel region. Here we make use of the well-known Berkeley BSIM 3v3 model. Whenever possible, we strive to not reinvent the wheel. In this case, we are trying to model a MOSFET channel which the BSIM model is well suited for. The model is physically based and accurately captures the transitions through sub-threshold, weak and strong inversions. Further, it has excellent speed and convergence of properties is widely available across multiple simulated platforms.
Figure 1 shows a typical cross-section of a silicon carbide MOSFET device. In Figure 2, we show a condensed version of our subcircuit model.
Next, we need to cover the critical gate to drain capacitor CGD formed by the poly overlap of the EPI region. This capacitor is essentially a highly nonlinear metal oxide semiconductor (MOS) capacitor. The depletion region of this capacitor is controlled by a complex dependence of the process parameters including the doping profile, the distance between the pwells dpw, and the thickness of the epitaxial layer. A physics-based model taking into account all of these effects is implemented in a SPICE agnostic behavioral approach. Later, we will discuss what a SPICE agnostic approach means later.
Turning from the cross-section, we would like to introduce some concepts and constructs behind our chip floorplan scalability as shown in Figure 3. The gray area is the active area. The blue non-active area is associated with the die edges, gate pad and gate runners. Physical geometry based derivations determine the distribution between non-active and active areas which is required to achieve scalability. We pay strong attention to the parasitic capacitances formed in the boundary regions between the active and non-active area. Once you start ignoring parasitic caps in the layout, when do you stop? All the negligible caps eventually add up and become a problem. One cannot achieve scaling in this case. Our philosophy is no capacitor left behind.
Silicon carbide MOSFETs support very fast dV/dts, around 50 to 100 volts per nanosecond, and dI/dts around 3 to 6 amps per nanoseconds. Intrinsic device gate resistance matters and can be used to combat EMI. The right design in Figure 3 has less gate runners and therefore higher RG; good to limit the ringing. The left design in Figure 3 has many gate runners, hence lower RG. The left design is good for fast switching, but also comes at a higher RDSon per area number since the gate runners eat away at the active area.
Read part three of our blog series that discusses the silicon carbide power MOSFET model verification.
