MOSFETs | FDC6321C

Dual N & P Channel Digital FET 25V

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Overview

These dual N & P Channel logic level enhancement mode field effect transistors are produced using a proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors in load switching applications. Since bias resistors are not required this dual digital FET can replace several digital transistors with different bias resistors.

  • This product is general usage and suitable for many different applications.
  • N-Ch 25 V, 0.68 A, RDS(ON) = 0.45 Ω @ VGS= 4.5 V
  • P-Ch -25 V, -0.46 A, RDS(ON) = 1.1 Ω @ VGS= -4.5 V.
  • Very low level gate drive requirements allowing direct operation in 3 V circuits. VGS(th) < 1.0V.
  • Gate-Source Zener for ESD ruggedness. >6kV Human Body Model
  • Replace multiple dual NPN & PNP digital transistors.

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CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

Channel Polarity

Configuration

V(BR)DSS Min (V)

VGS Max (V)

VGS(th) Max (V)

ID Max (A)

PD Max (W)

RDS(on) Max @ VGS = 2.5 V (mΩ)

RDS(on) Max @ VGS = 4.5 V (mΩ)

RDS(on) Max @ VGS = 10 V (mΩ)

Qg Typ @ VGS = 4.5 V (nC)

Qg Typ @ VGS = 10 V (nC)

Ciss Typ (pF)

Pricing ($/Unit)

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FDC6321C

Active

Pb

A

H

P

TSOT-23-6

419BL

1

260

REEL

3000

Y

Complementary

Dual

±25

-8

1.5

N: 0.68 , P: -0.46

0.9

N: 600, P:1500

N: 450, P:1100

-

-

1.1

63

$0.184

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