LVTTL/LVCMOS to Differential LVPECL Translator

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Overview

The MC100LVELT20 is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline SOIC−8 package and the single gate of the MC100LVELT20 makes it ideal for those applications where space, performance, and low power are at a
premium.
The 100 Series contains temperature compensation.

  • Single ended to differential level translation.
  • 390 ps Typical Propagation Delay
  • Maximum Input Clock Frequency > 0.8 GHz Typical
  • Operating Range VCC = 3.0 V to 3.6 Vwith GND = 0 V
  • PNP TTL Input for Minimal Loading
  • Pb-Free Packages are Available

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Product

Status

CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

Channels

Input Level

Output Level

VCC Typ (V)

fMax Typ (MHz)

tpd Typ (ns)

tR & tF Max (ps)

Reference Price

MC100LVELT20DG

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Active

CAD Model

Pb

A

H

P

SOIC-8

1

260

TUBE

98

Y

1

TTL

ECL

3.3

1000

0.37

225

Price N/A

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MC100LVELT20DR2G

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Active

CAD Model

Pb

A

H

P

SOIC-8

1

260

REEL

2500

Y

1

TTL

ECL

3.3

1000

0.37

225

Price N/A

More Details

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