PECL to NECL Translator

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Overview

The MC100EP91 is a triple AnyLevel™ positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential NECL output signals. VEE at -3.0 V to -5.5 V.

  • General Purpose Data and Clock Level Translation

  • Maximum Input Clock Frequency > 2.0 GHz Typical
  • Maximum Input Data Rate > 2.0 Gb/s Typical
  • 500 ps Typical Propagation Delay
  • Operating Range: VCC = 2.375 V to 3.8 V; VEE = 3.0 V to 5.5 V; GND = 0 V
  • Q Output will Default LOW with Inputs Open or at GND

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Product

Status

CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

Channels

Input Level

Output Level

VCC Typ (V)

fMax Typ (MHz)

tpd Typ (ns)

tR & tF Max (ps)

Reference Price

MC100EP91MNG

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CAD Model

Pb

A

H

P

QFN-24

1

260

TUBE

92

N

3

CML

CMOS

ECL

LVDS

TTL

ECL

3.3

2

0.5

250

Price N/A

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