ECL JK Flip-Flop

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Overview

The MC10EP35 is a higher speed/low voltage version of the EL35 JK flip flop. The JK data enters the master portion of the flip flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH.

The 100 Series contains temperature compensation.

  • Using ECL Logic technologies for reducing system clock skew over the alternative CMOS and TTL technologies.
  • 410 ps Propagation Delay
  • Maximum Frequency > 3 GHz Typical
  • PECL Mode Operatio Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0V to -5.5V
  • Open Input Default State
  • Q Output will default LOW with inputs open or at VEE
  • Pb-Free Packages are Available

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Product

Status

CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

Type

Bits

Input Level

Output Level

VCC Typ (V)

tJitter Typ (ps)

tpd Typ (ns)

tsu Min (ns)

th Min (ns)

trec Typ (ns)

tR & tF Max (ps)

fToggle Typ (MHz)

Reference Price

MC100EP35DTG

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Active

CAD Model

Pb

A

H

P

TSSOP-8

3

260

TUBE

100

N

JK-Type

1

ECL

ECL

3.3

0.2

0.41

0.15

0.15

0.15

170

3000

Price N/A

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