ECL D Flip-Flop with Set and Reset

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Overview

The MC10/100EP31 is a D flip-flop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices. With AC performance much faster than the EL31 and LVEL31 devices, the EP31 is ideal for applications requiring the fastest AC performance available. Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip-flop when CLK is low and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK.

The 100 Series contains temperature compensation.

  • Clock Distribution
  • 340ps Typical Propagation Delay
  • Maximum Frequency > 3 GHz Typical
  • PECL Mode Operating Range: VCC= 3.0 V to 5.5 V
    with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V
    with VEE= –3.0 V to –5.5 V
  • Open Input Default State
  • Q Output will default LOW with inputs open or at VEE
  • Pb-Free Packages are Available

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Product

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CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

Type

Bits

Input Level

Output Level

VCC Typ (V)

tJitter Typ (ps)

tpd Typ (ns)

tsu Min (ns)

th Min (ns)

trec Typ (ns)

tR & tF Max (ps)

fToggle Typ (MHz)

Reference Price

MC100EP31DG

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Active

CAD Model

Pb

A

H

P

SOIC-8

1

260

TUBE

98

Y

D-Type

1

CML

ECL

3.3

0.2

0.34

0.1

0.15

0.225

180

3000

Price N/A

More Details

MC100EP31DTG

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Active

CAD Model

Pb

A

H

P

TSSOP-8

3

260

TUBE

100

Y

D-Type

1

CML

ECL

3.3

0.2

0.34

0.1

0.15

0.225

180

3000

Price N/A

More Details

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