ECL 9-Bit Shift Register

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Overview

The MC10EP/100EP142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 - D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated.

The SEL (Select) input pin is used to switch between the two modes of operation - SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK0 or CLK1; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the resisters to zero.

The 100 Series contains temperature compensation.

  • Byte parity
  • > 3 GHz Minimum Shift Frequency
  • 9-Bit for Byte-Parity Applications
  • Asynchronous Master Reset
  • Dual Clocks
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = –3.0 V to –5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs

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Bits

Input Level

Output Level

VCC Typ (V)

tJitter Typ (ps)

tpd Typ (ns)

tsu Min (ns)

th Min (ns)

trec Typ (ns)

tR & tF Max (ps)

fToggle Typ (MHz)

Reference Price

MC100EP142FAG

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CAD Model

Pb

A

H

P

LQFP-32

2

260

JTRAY

250

Y

Shift Register

9

CML

ECL

3.3

1

0.675

0.05

0.1

0.8

250

2800

Price N/A

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