Clock & Data Distribution [Product View]

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Differential & Single-Ended CMOS, ECL, PECL, CML, LVDS, HSTL, HCSL

ON Semiconductor supplies high frequency single-ended CMOS devices; and devices based on Emitter Coupled Logic (ECL) design techniques, which provides superior jitter and skew. Devices are available in the PureEdge™, GigaComm™, ECLinPS MAX™, ECLinPS Plus™, ECLinPS Lite™, ECLinPS™, MECL-10KH™/MECL-100KH™, and MECL™ families.

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Arithmetic Functions  (41)
   
 

Counters - Dividers - Prescalers

Differential (ECL) arithmetic functions such as counters, dividers, and prescalers.
Technical Documentation & Design Resources
Application Notes (24) Package Drawings (15)
Simulation Models (60) Evaluation Board Documents (1)
Data Sheets (41) Evaluation Boards (8)
 
 
Drivers & Fanout Buffers  (150)
   
 
Differential (ECL) fanout buffers, clock drivers and signal drivers.

Technical Documentation & Design Resources
Application Notes (32) Package Drawings (30)
Simulation Models (170) Evaluation Boards (20)
Data Sheets (140)  
 
 
Flip-Flops, Latches & Registers  (55)
   
 

D FF - JK FF - Latch - Register - Shift Register

Differential (ECL) D flip-flops, JK flip-flops, latches, registers and shift registers.
Technical Documentation & Design Resources
Application Notes (25) Package Drawings (12)
Simulation Models (65) Evaluation Boards (1)
Data Sheets (41)  
 
 
Logic Gates  (37)
   
 
Differential (ECL) logic gates, including AND, NAND, OR, NOR, XOR, XNOR, and INV gates.
Technical Documentation & Design Resources
Application Notes (25) Data Sheets (35)
Simulation Models (55) Package Drawings (9)
 
 
Multiplexers & Crosspoint Switches  (60)
   
 
2:1, 4:1, 8:1, and 16:1 differential (ECL) multiplexers (MUXes), and 2:10 differential (ECL) crosspoint switches.
Technical Documentation & Design Resources
Application Notes (28) Package Drawings (16)
Simulation Models (70) Evaluation Boards (5)
Data Sheets (60)  
 
 
Serial / Parallel Converters  (6)
   
 
Differential (ECL) parallel-to-serial and serial-to-parallel converters.
Technical Documentation & Design Resources
Application Notes (18) Data Sheets (4)
Simulation Models (7) Package Drawings (3)
 
 
Skew Management  (11)
   
 
Programmable delay lines for clock skew management.
Technical Documentation & Design Resources
Application Notes (19) Package Drawings (4)
Simulation Models (10) Evaluation Boards (2)
Data Sheets (8)  
 
 
Translators  (46)
   
 

Logic Level Translators

Differential (ECL) logic level translators that interface with ECL, PECL, CML, LVDS, HSTL, HCSL, TTL, and CMOS devices.
Technical Documentation & Design Resources
Application Notes (25) Data Sheets (40)
Simulation Models (55) Package Drawings (14)
 
 
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NB7L1008  2.5 V / 3.3 V, 1:8 LVPECL Fanout Buffer

  • Typical maximum input data rate > 12 Gb/s
  • Typical RMS Additive Phase Jitter at 622MHz (12KHz-20MHz) : 25fs
  • Low output to output skew, < 20 ps (max)

NB7L1008  2.5 V / 3.3 V, 1:8 LVPECL Fanout Buffer

  • Typical maximum input data rate > 12 Gb/s
  • RMS Additive Phase Jitter at 622 MHz (12 KHz-20 MHz) : 25 fs
  • Low output to output skew, < 20 ps max