Clock & Data Distribution [Product View]

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Differential & Single-Ended CMOS, ECL, PECL, CML, LVDS, HSTL, HCSL

ON Semiconductor supplies high frequency single-ended CMOS devices; and devices based on Emitter Coupled Logic (ECL) design techniques, which provides superior jitter and skew. Devices are available in the PureEdge™, GigaComm™, ECLinPS MAX™, ECLinPS Plus™, ECLinPS Lite™, ECLinPS™, MECL-10KH™/MECL-100KH™, and MECL™ families.

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Arithmetic Functions  (41)
   
 

Counters - Dividers - Prescalers

Differential (ECL) arithmetic functions such as counters, dividers, and prescalers.
Technical Documentation & Design Resources
Application Notes (24) Package Drawings (15)
Simulation Models (60) Evaluation Board Documents (1)
Data Sheets (41) Evaluation/Development Tools (8)
 
 
Flip-Flops, Latches & Registers  (56)
   
 

D FF - JK FF - Latch - Register - Shift Register

Differential (ECL) D flip-flops, JK flip-flops, latches, registers and shift registers.
Technical Documentation & Design Resources
Application Notes (25) Package Drawings (12)
Simulation Models (65) Evaluation/Development Tools (1)
Data Sheets (41)  
 
 
Logic Gates  (37)
   
 
Differential (ECL) logic gates, including AND, NAND, OR, NOR, XOR, XNOR, and INV gates.
Technical Documentation & Design Resources
Application Notes (25) Data Sheets (35)
Simulation Models (55) Package Drawings (9)
 
 
Multiplexers & Crosspoint Switches  (59)
   
 
2:1, 4:1, 8:1, and 16:1 differential (ECL) multiplexers (MUXes), and 2:10 differential (ECL) crosspoint switches.
Technical Documentation & Design Resources
Application Notes (28) Package Drawings (16)
Simulation Models (70) Evaluation/Development Tools (5)
Data Sheets (59)  
 
 
Serial / Parallel Converters  (6)
   
 
Differential (ECL) parallel-to-serial and serial-to-parallel converters.
Technical Documentation & Design Resources
Application Notes (18) Data Sheets (4)
Simulation Models (7) Package Drawings (3)
 
 
Skew Management  (9)
   
 
Programmable delay lines for clock skew management.
Technical Documentation & Design Resources
Application Notes (19) Package Drawings (4)
Simulation Models (10) Evaluation/Development Tools (2)
Data Sheets (8)  
 
 
Translators  (47)
   
 

Logic Level Translators

Differential (ECL) logic level translators that interface with ECL, PECL, CML, LVDS, HSTL, HCSL, TTL, and CMOS devices.
Technical Documentation & Design Resources
Application Notes (25) Data Sheets (41)
Simulation Models (55) Package Drawings (16)
 
 
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NB3L8504S  2.5 V / 3.3 V 1:4 Differential Input to LVDS Fanout Buffer / Translator

  • 50 ps maximum output skew
  • 1.3 ns maximum propagation delay
  • Accept LVPECL, LVDS, HSTL, HCSL and SSTL

NB3N1900K  NB3W1900L  3.3V 100/133 MHz Differential 1:19 HCSL Clock ZDB/Fanout Buffer for PCIe

  • 19 differential clock output pairs @ 0.7 V
  • Optimized 100 MHz and 133 MHz operating frequencies to meet the next generation PCIe Gen 2/Gen 3 and Intel QPI phase jitter
  • 3.3 V ±5% supply voltage operation