RSL10 SPI data delays between CS and Actual Data Transfer

Connectivity Bluetooth Low Energy
#1

Hello,
I am working with an external SPI peripheral to send and retrieve data from. The code is written in On Semi’s IDE and with the RSL10 drivers used (version 3.5.285) and the ARM CMSIS Drivers (5.8.0).

The SPI module used is SPI0 and the default pins are used for data transfer :

    .default_cfg = {                                               /* spi0 default configuration */
        .sclk_pin            = RTE_SPI0_SCLK_PIN_DEFAULT,          /* spi0 default sclk pin */
        .ssel_pin            = RTE_SPI0_SSEL_PIN_DEFAULT,          /* spi0 default ssel pin */
        .miso_pin            = RTE_SPI0_MISO_PIN_DEFAULT,          /* spi0 default miso pin */
        .mosi_pin            = RTE_SPI0_MOSI_PIN_DEFAULT,          /* spi0 default mosi pin */

And the SPI0 module is set as MASTER with a clock set to 6MHz :

    spi0->Control(ARM_SPI_MODE_MASTER,6000000);
    spi0->Control(ARM_SPI_SS_MASTER_HW_OUTPUT,0);
    spi0->PowerControl(ARM_POWER_FULL);

The CS Pin is set to low when a data transfer is requested.

I am sending 16-bit words over SPI and these words are stocked into a buffer that I am sending all at once, the function used :

void drv_spi_send_table(uint16_t *tabSPIBuffer, uint16_t BufferSize)
{
     for (int bufferIndex =0; bufferIndex<BufferSize; bufferIndex++)
    {
        spi0->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_ACTIVE);
        spi0->Transfer(tabSPIBuffer + bufferIndex,NULL,NUMBER_OF_DATA_BYTES);
        spi0->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_INACTIVE);
    }
}

(NUMBER_OF_DATA_BYTES is equal to 2 since i am sending 16-bit words)

But when I am sending Data over SPI to the external peripheral, i am noticing a substancial delay between the driving of the CS to the Low Logic Level and the actual data transfer (On a Logic Analyzer).
There is also a delay after the end of the data transfer to the driving of the CS to the High logic level ( peripiheral needs this to accept the following 16-bit word in the buffer) :

Delay between the CS being driven low and the start of the Data Transfer
Delay between the CS being driven low and the start of the Data Transfer1854×586 37.8 KB

I tried minimizing callback overheads by directly accessing the ARM_DRIVER_SPI Driver_SPI0 structure used in the SPI_RSLxx.c file.

Does anyone have a recommandation to reduce this delay ?

Thanks in advance.

#5

@User341

Please try the following suggestions :

  • When the SPI Driver is configured to function as a Master, the driver should automatically set the CS when you call the ‘Transfer()’ function. Can you please try removing the first call to ‘Control()’ and checking if this saves you any additional cycles?

  • Given the ‘Transfer()’ call is non-blocking I do not believe the code above will behave as expected. Our usual suggestion is to call the ‘Transfer()’ function and then use the SPI Transfer Complete Event to reset the CS. Another option is to simply poll the SPI Status bit to check if the transfer is complete before clearing the CS and moving on with the code.

  • If the CMSIS Driver version of the SPI Driver is causing unnecessary delay, it is always possible to write an SPI driver for your specific firmware that does not have nearly as much overhead as a generalized driver. We can help with this if needed.

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