I have working on PCM Interface of RSL10.I have set to RSL10 as slave (in I2S Protocol) then ı have choosen CM3 (Cortex M3) as controller of PCM Interface with PCM_TX_IRQ interrupt.
There is some information about that interrupt handler In RSL10 hardware document on page 326;
“The PCM transmit and receive interrupts are generated for every word of data transmitted in a valid PCM frame regardless of the length of the PCM frame”…
Lets think about this;
We have (for example) 24kHz LRCLK(Left-right clock-so 24kHz sample rate) signals.So,RSL10 must go to interrupt 240002 (sample rateWord (as you know we have 2 word left and right on I2S protocol)) times for every seconds.
When ı zoom on this interrupt with uint32_t count variable for a one second, ı have see that value equal to 6800…Is that value maximum sample rate of PCM Interface of RSL10? (I don’t think so…)…
When ı have changed clock byte of 48 Mhz (for example : RF_REG2F->CK_DIV_1_6_CK_DIV_1_6_BYTE = CK_DIV_1_6_PRESCALE_1_BYTE; ) this count value goes to down but never goes to above 6800. I mean 6800 values come with 48 Mhz clock if ı change this value CK_DIV_1_6_PRESCALE_1_BYTE " count "value goes to down…
My PCM and clock configurations follows below;
RF_REG2F->CK_DIV_1_6_CK_DIV_1_6_BYTE = CK_DIV_1_6_PRESCALE_1_BYTE;
Sys_Clocks_SystemClkConfig(JTCK_PRESCALE_1 |EXTCLK_PRESCALE_1 | SYSCLK_CLKSRC_RFCLK);
Sys_Clocks_SystemClkPrescale1(PWM0CLK_PRESCALE_1 | PWM1CLK_PRESCALE_1 |UARTCLK_PRESCALE_1 | AUDIOCLK_PRESCALE_1 |AUDIOSLOWCLK_PRESCALE_1);
Sys_PCM_ConfigClk(PCM_SELECT_SLAVE, DIO_WEAK_PULL_UP, 0, 1, 9, 4, DIO_MODE_INPUT);
PCM_CFG_TX (PCM_BIT_ORDER_MSB_FIRST |
So, Can you help me about this issue?How can ı increase of PCM_TX_IRQ handler numbers?