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NB3L208KMNGEVB: 1:8 HCSL Fanout Buffer Evaluation Board

The NB3L208KMNGEVB evaluation board is designed to test and evaluate the NB3L208K, which is a differential 1:8 Clock fanout buffer with High-speed Current Steering Logic (HCSL) outputs. Inputs can directly accept differential LVPECL, LVDS and HCSL signals. Single-ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external VTH reference supply. These signals will be translated to HCSL and eight identical copies of Clock will be distributed, operating up to 350 MHz.
Evaluation/Development Tool Information
Product Status Compliance Short Description Parts Used Action
NB3L208KMNGEVB Active
1:8 HCSL Fanout Buffer Evaluation Board NB3L208KMNG
Technical Documents
Type Document Title Document ID/Size Rev
Eval Board: Manual NB3L208K Evaluation Board User's Manual EVBUM2295/D - 424 KB  1 
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