Altium

Design Rule Verification Report

Date:		10/19/2015
Time:		2:05:14 PM
Elapsed Time:		00:00:01
Filename:		C:\Projects\zigbee\trunk\hw\Orion\pcb\Motherboard\jackpot\jackpot.PcbDoc

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Net Antennae (Tolerance=0mm) (All)	0
Silk primitive without silk layer	0
Silk to Silk (Clearance=0.254mm) (Disabled)(All),(All)	0
Silk To Solder Mask (Clearance=0.254mm) (Disabled)(IsPad),(All)	0
Minimum Solder Mask Sliver (Gap=0.254mm) (Disabled)(All),(All)	0
Hole To Hole Clearance (Gap=0.254mm) (All),(All)	0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)	0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)	0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)	0
Hole Size Constraint (Min=0.203mm) (Max=6.375mm) (All)	0
Minimum Annular Ring (Minimum=0.178mm) (All)	0
Un-Routed Net Constraint ( (All) )	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Power Plane Connect Rule(Direct Connect )(Expansion=0.254mm) (Conductor Width=0.203mm) (Air Gap=0.254mm) (Entries=4) (All)	0
Width Constraint (Min=0.152mm) (Max=2.54mm) (Preferred=0.254mm) (All)	0
Clearance Constraint (Gap=0.152mm) (All),(All)	0
Total	0