Hex D Flip-Flop with Common Clock and Reset

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Overview

This device consists of six flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-tohigh transition; of the Clock input. Reset is asynchronous and active low. All inputs/outputs are standard CMOS compatible.

  • Output Drive Compatibility: 10 LSTTL Loads
  • Outpus Directly Interface to CMOS
  • Operation Voltage Range: 2 to 6 V
  • Low Input Current: 1.0 µ A
  • MSL Level 1
  • Chip Complexity: 162 FET
  • Pb-Free Package is Available

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Product

Status

CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

Type

Channels

VCC Min (V)

VCC Max (V)

tpd Max (ns)

IO Max (mA)

Pricing ($/Unit)

NLSF1174MNR2G

Active

CAD Model

Pb

A

H

P

QFN-16

1

260

REEL

3000

Y

D-Type

2

2

6

20

4

$0.1693

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