Hex D Flip-Flop with Common Clock and Reset

Overview

This device consists of six flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-tohigh transition; of the Clock input. Reset is asynchronous and active low. All inputs/outputs are standard CMOS compatible.

  • Output Drive Compatibility: 10 LSTTL Loads
  • Outpus Directly Interface to CMOS
  • Operation Voltage Range: 2 to 6 V
  • Low Input Current: 1.0 µ A
  • MSL Level 1
  • Chip Complexity: 162 FET
  • Pb-Free Package is Available

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NLSF1174MNR2G

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Lifetime

CAD Model

Pb

A

H

P

QFN-16

1

260

REEL

3000

Y

D-Type

2

2

6

20

4

$0.2052

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