D Flip-Flops and JK Flip-Flops | MC74ACT377

Octal D Flip-Flop with Clock Enable

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Overview

The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flipflop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

  • Ideal for Addressable Register Applications
  • Clock Enable for Address and Data Synchronization Applications
  • Eight Edge-Triggered D Flip-Flops
  • Buffered Common Clock
  • Outputs Source/Sink 24 mA
  • See MC74AC273 for Master Reset Version
  • See MC74AC373 for Transparent Latch Version
  • See MC74AC374 for 3-State Version
  • ACT377 Has TTL Compatible Inputs
  • Pb-Free Packages are Available

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MC74ACT377DWG

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Obsolete

CAD Model

Pb

A

H

P

SOIC-20W

751D-05

3

260

TUBE

38

N

D-Type

8

4.5

5.5

10

24

Price N/A

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MC74ACT377DWR2G

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Active

CAD Model

Pb

A

H

P

SOIC-20W

751D-05

3

260

REEL

1000

N

D-Type

8

4.5

5.5

10

24

$0.4067

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Reliability Data

Die Related Summary Data

Device: MC74ACT377DWG

Equivalent to wafer fab process: CMOS SUB

Product Technology

Product Technology

Equivalent Device-Hours

MTBF/MTTF in Hours

FITS

CMOS SUB

2

920154574

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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