3.3 V 100/133 MHz Differential 1:19 HCSL Clock ZDB/Fanout Buffer for PCIe

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Overview

The NB3N1900K differential clock buffers are designed to work inconjunction with a PCIe compliant source clock synthesizer to providepoint−to−point clocks to multiple agents. The device is capable ofdistributing the reference clocks for Intel® QuickPath Interconnect(Intel QPI & UPI), PCIe Gen1, Gen2, Gen3, Gen4. The NB3N1900K internal PLL isoptimized to support 100 MHz and 133 MHz frequency operation.The NB3N1900K supports HCSL output levels.

  • Industrial
  • Networking
  • Computing
  • Consumer
  • PCIe Gen 1, Gen 2, Gen 3, Gen 4
  • Desktop
  • Notebook
  • Switchers/Routers
  • Servers
  • Set Top Box
  • Automated Test Equipment
  • Fixed Feedback Path for Lowest Input−to−Output Delay
  • Eight Dedicated OE# Pins for Hardware Control of Outputs
  • PLL Bypass Configurable for PLL or Fanout Operation
  • Selectable PLL Bandwidth
  • Spread Spectrum Compatible: Tracks Input Clock Spreading for LowEMI
  • SMBus Programmable Configurations
  • 100 MHz and 133 MHz PLL Mode to Meet the Next Generation PCIe Gen2 / Gen 3 /Gen 4 and Intel QPI & UPI Phase Jitter
  • 2 Tri−Level Addresses Selection (Nine SMBUS Addresses)
  • Cycle−to−Cycle Jitter: < 50 ps
  • Output−to−Output Skew: < 65 ps
  • Input−to−Output Delay: Fixed at 0 ps
  • Input−to−Output Delay Variation: < 50 ps
  • Phase Jitter: PCIe Gen3 < 1 ps rms
  • Phase Jitter: PCIe Gen4 < 0.5 ps rms
  • Phase Jitter: QPI 9.6GB/s < 0.2 ps rms
  • QFN 72−pin Package, 10 mm x 10 mm
  • These are Pb−Free Devices

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Reference Price

NB3N1900KMNTWG

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Active

CAD Model

Pb

A

H

P

QFN-72

3

260

REEL

1000

Y

HCSL

HCSL

19

3.3

85

133.33

50

Price N/A

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