Phase-Locked LoopHigh−Performance Silicon−Gate CMOS

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Overview

The MC74HC4046B is similar in function to the MC14046 Metalgate CMOS device. The device inputs are compatible with standardCMOS outputs; with pullup resistors, they are compatible withLSTTL outputs.The HC4046B phase−locked loop contains three phasecomparators, a voltage−controlled oscillator (VCO) and unity gainop−amp DEMOUT. The comparators have two common signal inputs,COMPIN, and SIGIN. Input SIGIN and COMPIN can be used directlycoupled to large voltage signals, or indirectly coupled (with a seriescapacitor to small voltage signals). The self−bias circuit adjusts smallvoltage signals in the linear region of the amplifier. Phase comparator1 (an exclusive OR gate) provides a digital error signal PC1OUT andmaintains 90 degrees phase shift at the center frequency betweenSIGIN and COMPIN signals (both at 50% duty cycle). Phasecomparator 2 (with leading−edge sensing logic) provides digital errorsignals PC2OUT and PCPOUT and maintains a 0 degree phase shiftbetween SIGIN and COMPIN signals (duty cycle is immaterial). Thelinear VCO produces an output signal VCOOUT whose frequency isdetermined by the voltage of input VCOIN signal and the capacitorand resistors connected to pins C1A, C1B, R1 and R2. The unity gainop−amp output DEMOUT with an external resistor is used where theVCOIN signal is needed but no loading can be tolerated. The inhibitinput, when high, disables the VCO and all op−amps to minimizestandby power consumption.Applications include FM and FSK modulation and demodulation,frequency synthesis and multiplication, frequency discrimination,tone decoding, data synchronization and conditioning, voltage−to−frequency conversion and motor speed control.

  • Output Drive Capability: 10 LSTTL Loads
  • Low Power Consumption Characteristic of CMOS Devices
  • Operating Speeds Similar to LSTTL
  • Wide Operating Voltage Range for VCO: 3.0 to 6.0 V
  • Low Input Current: 1.0 A Maximum (except SIGIN and COMPIN)
  • In Compliance with the Requirements Defined by JEDEC StandardNo. 7 A
  • Low Quiescent Current: 80 A Maximum (VCO disabled)
  • High Noise Immunity Characteristic of CMOS Devices
  • Diode Protection on All Inputs
  • Chip Complexity: 279 FETs or 70 Equivalent Gates

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MC74HC4046BDTR2G

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TSSOP-16

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