PLL Clock Generators | NB3H5150

Clock Generator, Multi-Rate, Low Noise 2.5V / 3.3V

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Overview

The NB3H5150 is a high performance Multi−Rate Clock generatorwhich simultaneously synthesizes up to four different frequenciesfrom a single PLL using a 25 MHz input reference. The referencefrequency can be provided by a crystal, LVCMOS/LVTTL, LVPECL,HCSL or LVDS differential signals. The REFMODE pin will selectthe reference source.Three output banks (CLK1A/CLK1B to CLK3A/CLK3B) produceuser selectable frequencies of: 25 MHz, 33.33 MHz, 50 MHz,100 MHz, 125 MHz, or 156.25 MHz and have ultra−low noise/jitterperformance of less than 0.3 ps.The fourth output bank (CLK4A/CLK4B) can produce thefollowing integer and FRAC−N frequencies in pin−strap mode:33.33 MHz, 66.66 MHz, 100 MHz, 106.25 MHz, 125 MHz,133.33 MHz, 155.52 MHz, 156.25 MHz or 161.1328 MHz.More programmable frequencies are available via the I2C interfacewith jitter performance of less than 1 ps. Detailed registereddescriptions will be available in a future application note.Each output block can create two single−ended in−phase LVCMOSoutputs or one differential pair of LVPECL outputs.Each of the four output blocks is independently powered by aseparate VDDO, 2.5 V/3.3 V for LVPECL, 1.8 V/2.5 V/3.3 V forLVCMOS.The serial (I2C and SMBUS) interface can program a variety offunctions including the frequencies and output levels of each dividerblock which can be individually enabled and disabled.

  • Telecom
  • Networking
  • Ethernet
  • SONET

  • Solid State Hard Drive

  • Flexible Input Reference − 25 MHz Crystal, Oscillator, Single−Ended or Differential
  • Four Independent User−Programmable Clock Frequencies from 25 MHz to 250 MHz
  • Independently Configurable Outputs:
  • Up to Eight LVCMOS Single Ended outputs or,
  • Up to Four Differential LVPECL Outputs or any combination of LVCMOS and LVPECL
  • Flexible Input/Core and Output Power Supply Combinations:
  • VDD (Core) = 3.3 V ±5% or 2.5 V ±5%
  • VDDOn (Outputs) = 3.3 V ±5% or 2.5 V ±5% or 1.8 V ±5% (LVCMOS Only)
  • Independent Power Supply per Output Bank
  • 300 ps max Output Rise and Fall Times, LVPECL
  • 1000 ps max Output Rise and Fall Times, LVCMOS
  • 300 fs maximum RMS Phase Jitter (CLK1:4) Integer-N
  • 1 ps maximum RMS Phase Jitter (CLK4) Frac-N
  • I2C / SMBus Compatible Interface
  • −40°C to +85°C Ambient Operating Temperature
  • 32−Pin QFN, 5 mm x 5 mm
  • Zero ppm Multiplication Error
  • Fractional Divide Ratios for Implementing Arbitrary FEC/Inverse−FEC Ratios
  • This is a Pb−Free Device

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NB3H5150MNTXG

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CAD Model

Pb

A

H

P

QFN-32

485CE

1

260

REEL

1000

Y

TTL

LVPECL

3.3

25

25-250

-

-

0.5

800

300

-40

85

Price N/A

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Reliability Data

Die Related Summary Data

Device: NB3H5150MNTXG

Equivalent to wafer fab process: ONC18

Product Technology

Product Technology

Equivalent Device-Hours

MTBF/MTTF in Hours

FITS

ONC18

2

6465777234

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Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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