Translator, AnyLevel™ Positive Input to NECL Output Voltage

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Overview

The NB100LVEP91 is a triple input to NECL output translator. The device accepts LVPECL, LVTTL, HSTL, CML or LVDS signals, and translates them to differential -2.5 V / -3.3 V NECL output signals.

To accomplish the level translation, the LVEP91 requires three power rails. The VCC supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply. The GNDI pins are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.01 uF capacitors.

Under open input conditions, the Dbar input will be biased at VCC/2 and the D input will be pulled to GND. This condition will force the Q output to a low, ensuring stability.

The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

  • Typical Maximum Frequency >2 GHz
  • 430 ps Typical Propagation Delay
  • Operating Range: VCC = 2.375 V to 3.8 V; VEE = -2.375 V to -3.8 V; GNDI = 0 V
  • Q Output will default LOW with Inputs Open or at GND
  • Pb-Free Packages are Available

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VCC Typ (V)

fMax Typ (MHz)

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Reference Price

NB100LVEP91DWG

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Active

CAD Model

Pb

A

H

P

SOIC-20W

3

260

TUBE

38

Y

3

LVDS

ECL

3.3

2500

0.5

250

Price N/A

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NB100LVEP91MNG

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Active

CAD Model

Pb

A

H

P

QFN-24

1

260

TUBE

92

Y

3

LVDS

ECL

3.3

2500

0.5

250

Price N/A

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