Translator, 10-bit LVTTL / LVCMOS to LVPECL

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Overview

The MC100EPT622 is a 10-Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL (Positive ECL) levels are used, only +3.3 V and ground are required. The device has an OR-ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs (ENTTL). If the inputs are left open, they will default to the enable state. The device design has been optimized for low channel-to-channel skew.

  • 450 ps Typical Propogation Delay
  • Maximum Frequency > 1.5 GHz Typical
  • PECL Mode
  • Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V
  • PNP LVTTL Inputs for Minimal Loading
  • Q Outputs Will Default HIGH with Inputs Open
  • The 100 Series Contains Temperature Compensation

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CAD Models

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Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

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ON Target

Channels

Input Level

Output Level

VCC Typ (V)

fMax Typ (MHz)

tpd Typ (ns)

tR & tF Max (ps)

Reference Price

MC100EPT622FAG

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Active

CAD Model

Pb

A

H

P

LQFP-32

2

260

JTRAY

250

Y

10

TTL

ECL

3.3

1500

0.5

450

Price N/A

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MC100EPT622MNG

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Active

CAD Model

Pb

A

H

P

QFN-32

1

260

TUBE

74

Y

10

TTL

ECL

3.3

1500

0.5

450

Price N/A

More Details

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