MC100EPT622

Translator, 10-bit LVTTL / LVCMOS to LVPECL

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CAD Model

Overview

The MC100EPT622 is a 10-Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL (Positive ECL) levels are used, only +3.3 V and ground are required. The device has an OR-ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs (ENTTL). If the inputs are left open, they will default to the enable state. The device design has been optimized for low channel-to-channel skew.

Features

450 ps Typical Propogation Delay
Maximum Frequency > 1.5 GHz Typical
PECL Mode
Operating Range: V_CC = 3.0 V to 3.8 V with V_EE = 0 V
PNP LVTTL Inputs for Minimal Loading
Q Outputs Will Default HIGH with Inputs Open
The 100 Series Contains Temperature Compensation

Material Composition

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Package Type

Case Outline

MSL Type

MSL Temp (°C)

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Container Qty.

Channels

Input Level

Output Level

V_CC Typ (V)

f_Max Typ (MHz)

t_pd Typ (ns)

t_R & t_F Max (ps)

Pricing ($/Unit)

MC100EPT622MNG

Active

QFN-32

488AM

260

TUBE

TTL

ECL

3.3

1500

0.5

450

Price N/A

MC100EPT622FAG

Active

LQFP-32

561AB

260

JTRAY

250

TTL

ECL

3.3

1500

0.5

450

Price N/A

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Translators | MC100EPT622

Translator, 10-bit LVTTL / LVCMOS to LVPECL

Overview

Availability & Samples (size)

Email Sales