MC100EP196: 3.3 V ECL Programmable Delay Chip

Datasheet: 3.3V ECL Programmable Delay Chip with FTUNE
Rev. 16 (145kB)
Product Overview
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Product Change Notification
The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from VCC to VEE to fine tune the output delay from 0 to 60 ps.
Features
 
  • Maximum Frequency > 1.2 GHz Typical
  • PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • A Logic High on the ENbar Pin Will Force Q to Logic Low
  • D[0:10] Can Accept Either ECL, LVCMOS, or LVTTL Inputs
  • VBB Output Reference Voltage
  • Pb-Free Packages are Available
Availability & Samples
Specifications
Case Outlines
Interactive Block Diagram
Product
Status
Compliance
Description
Package
MSL
Container
Budgetary Price/Unit
Type
Case Outline
Type
Temperature
Type
Qty.
MC100EP196FAG Active
Pb-free
Halide free
MC100EP196 LQFP-32 561AB 2 260 Tray JEDEC 250 $7.0
MC100EP196FAR2G Active
Pb-free
Halide free
MC100EP196 LQFP-32 561AB 2 260 Tape and Reel 2000 $7.0
Market Leadtime (weeks) : 17 to 20
Avnet   (2020-08-19 00:00) : <100
PandS   (2020-09-14 00:00) : <100
Market Leadtime (weeks) : Contact Factory

Product
Description
Pricing ($/Unit)
Compliance
Status
Input Level
Output Level
VCC Typ (V)
fMax Typ (MHz)
td(prog) Min (ns)
td(prog) Max (ns)
td(step) Typ (ps)
tJitter Typ (ps)
tR & tF Max (ps)
Package Type
MC100EP196FAG  
 $7.0 
Pb
H
 Active   
CML
ECL
ECL
3.3
1200
8.6
12
11
3
200
LQFP-32
MC100EP196FAR2G  
 $7.0 
Pb
H
 Active   
CML
ECL
ECL
3.3
1200
8.6
12
11
3
200
LQFP-32
Case Outlines
561AB   
Packages
MC100EP196: 3.3 V ECL Programmable Delay Chip
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