3.3 V ECL Programmable Delay Chip

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Overview

The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from VCC to VEE to fine tune the output delay from 0 to 60 ps.

  • Maximum Frequency > 1.2 GHz Typical
  • PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • A Logic High on the ENbar Pin Will Force Q to Logic Low
  • D[0:10] Can Accept Either ECL, LVCMOS, or LVTTL Inputs
  • VBB Output Reference Voltage
  • Pb-Free Packages are Available

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CAD Models

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Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

Input Level

Output Level

VCC Typ (V)

fMax Typ (MHz)

td(prog) Min (ns)

td(prog) Max (ns)

td(step) Typ (ps)

tJitter Typ (ps)

tR & tF Max (ps)

Reference Price

MC100EP196FAG

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Active

CAD Model

Pb

A

H

P

LQFP-32

2

260

JTRAY

250

Y

ECL

ECL

3.3

1200

8.6

12

11

3

200

Price N/A

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MC100EP196FAR2G

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Active

CAD Model

Pb

A

H

P

LQFP-32

2

260

REEL

2000

Y

ECL

ECL

3.3

1200

8.6

12

11

3

200

Price N/A

More Details

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