Flip-Flops, Latches & Registers | NB4L52

2.5 to 5.5 V ECL D Flip-flop w/Differential Reset & Input Termination

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Overview

The NB4L52 is a differential Data and Clock D flip−flop with a differential asynchronous Reset. The differential inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock transitions from Low to High, Data will be transferred to the differential LVPECL outputs. The differential Clock inputs allow the NB4L52 to also be used as a negative edge triggered device. The device is housed in a small 3mm x 3mm 16 pin QFN package.

  • High Performance Logic for ATE and Networking
  • Maximum Input Clock Frequency > 4 GHz Typical
  • 330 ps Typical Propagation Delay
  • 145 ps Typical Rise and Fall Times
  • Differential LVPECL Outputs, 750 mV PeaktoPeak, Typical
  • Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V

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Package Type

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MSL Type

MSL Temp (°C)

Container Type

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ON Target

Type

Bits

Input Level

Output Level

VCC Typ (V)

tJitter Typ (ps)

tpd Typ (ns)

tsu Min (ns)

th Min (ns)

trec Typ (ns)

tR & tF Max (ps)

fToggle Typ (MHz)

Pricing ($/Unit)

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NB4L52MNR2G

Active

Pb

A

H

P

QFN-16

485G-01

1

260

REEL

3000

Y

D-Type

1

LVDS

ECL

5

1

0.4

0.1

0.05

0.4

190

4000

Price N/A

More Details

NB4L52MNG

Active

Pb

A

H

P

QFN-16

485G-01

1

260

TUBE

123

Y

D-Type

1

LVDS

ECL

5

1

0.4

0.1

0.05

0.4

190

4000

Price N/A

More Details

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