Fanout Buffer, Equalizer Receiver, 10 Gbps, 1.8 V / 2.5 V, with 1:6 Differential CML Outputs

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Overview

The NB7VQ1006M is a high performance EQualizer Receiver (signal enhancer) that operates up to 10 Gbps/7.5 GHz with a 1.8 V or 2.5 V power supply. When placed in series with a Data/Clock path, it will enhance the degraded signal transmitted across a FR4 backplane or cable interconnect and output six identical CML copies of the input signal. The EQualizer ENable pin (EQEN) allows the IN/IN inputs to either flow through or bypass the EQualizer section. Control of the EQualizer function is realized by setting EQEN. When EQEN is set Low, the IN / IN inputs bypass the Equalizer. When EQEN is set High, the IN / IN inputs flow through the EQualizer. The default state at start-up is LOW. The differential Data/Clock inputs incorporate a pair of internal 50-ohm termination resistors, in a 100-ohm center-tapped configuration, via the VT Pin and will accept differential LVPECL, CML or LVDS logic levels. This feature provides transmission line termination on-chip, at the receiver end, eliminating external components. The NB7VQ1006M is a member of the PEEQ GigaComm™ family of high performance Data/Clock products.

  • Backplane and Cable Interconnect Compensation
  • Maximum Input Data Rate > 10 Gbps
  • Maximum Input Clock Frequency > 7.5 GHz
  • Backplane and Cable Interconnect Compensation
  • Differential CML Outputs, 400 mV Peak-to-Peak, Typical
  • Operating Range: VCC = 1.71 V to 2.625 V, GND = 0 V
  • -40°C to +85°C Ambient Operating Temperature

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NB7VQ1006MMNG

Active

Pb

A

H

P

QFN-24

1

260

TUBE

92

Y

Signal Driver

1

1:6

LVDS

CML

2.5

0.2

25

0.225

65

7500

10000

Price N/A

More Details

NB7VQ1006MMNTXG

Active

Pb

A

H

P

QFN-24

1

260

REEL

3000

Y

Signal Driver

1

1:6

LVDS

CML

2.5

0.2

25

0.225

65

7500

10000

Price N/A

More Details

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