NB4N121K: Clock Fanout Buffer, 1:21 Differential, 3.3 V, with HCSL Level Output

Datasheet: Clock Fanout Buffer, 1:21 Differential, 3.3 V, with HCSL Level Output
Rev. 7 (146.0kB)
Product Overview
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The NB4N121K is a Clock differential input fanout distribution 1 to 21 HCSL level differential outputs, optimized for ultra low propagation delay variation. The NB4N121K is designed with HCSL clock distribution for FBDIMM applications in mind. Inputs can accept differential LVPECL, CML, or LVDS levels. Single-ended LVPECL, CML, LVCMOS or LVTTL levels are accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12, and 13). Clock input pins incorporate an internal 50 ohm on die termination resistors.
Features   Benefits
     
  • Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and400 MHz
 
  • Meets wide range of FBDIMM bus frequencies
  • <1 ps RMS Additive Clock jitter
 
  • Best in class for jitter performance
  • Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
 
  • Ensures operation in the majority of designs
  • 340 ps Typical Rise and Fall Times
   
  • 800 ps Typical Propagation Delay tPD 100 ps Maximum Propagation
   
  • Delta tPD 100 ps Maximum Propagation Delay Variation Per Each Differential Pair
   
  • Differential HCSL Output Level (700 mV Peak-to-Peak)
   
Applications   End Products
  • FBDIMM Clock Distribution
  • PCIe I, II, II
  • Networking
  • Clock Distribution
  • High End Computing
 
  • FBDIMM Memory Support
  • Servers
  • Routers
Technical Documentation & Design Resources
Simulation Models (1) Package Drawings (1)
Data Sheets (1)  
Availability & Samples
Specifications
Interactive Block Diagram
Product
Status
Compliance
Description
Package
MSL
Container
Budgetary Price/Unit
Type
Case Outline
Type
Temperature
Type
Qty.
NB4N121KMNR2G Active
Pb-free
Halide free
NB4N121K QFN-52 485M 1 260 Tape and Reel 2000 $4.0
Market Leadtime (weeks) : Contact Factory

Product
Description
Pricing ($/Unit)
Compliance
Status
Type
Channels
Input / Output Ratio
Input Level
Output Level
VCC Typ (V)
tJitterRMS Typ (ps)
tskew(o-o) Max (ps)
tpd Typ (ns)
tR & tF Max (ps)
fmaxClock Typ (MHz)
fmaxData Typ (Mbps)
Package Type
NB4N121KMNR2G  
 $4.0 
Pb
H
 Active   
Buffer
1
1:21
CML
CMOS
ECL
LVDS
TTL
HCSL
3.3
1
50
0.8
700
200
QFN-52
Case Outlines
485M   
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