Xtal Input or LVTTL / LVCMOS Input Mux - 2:1, 3.3 V, Fanout Buffer- 1:4 LVPECL

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Overview

The NB3N853531E is a low skew 3.3 V supply 2:1:4 clock distribution fanout buffer. An input MUX selects either a Fundamental Parallel Mode Crystal or a LVCMOS/LVTTL Clock by using the CLK_SEL pin (HIGH for Crystal, LOW for Clock) with LVCMOS / LVTTL levels. The single ended CLK input is translated to four LVPECL Outputs. Using the crystal input, the NB3N853531E can be a Clock Generator. A CLK_EN pin can enable or disable the outputs synchronously to eliminate runt pulses using LVCMOS/LVTTL levels (HIGH to enable outputs, LOW to disable output).

  • Gigibit Ethernet
  • SONET/SDH
  • Teleconmmunications

  • LAN/WAN
  • Enterprise Servers
  • ATE
  • Test and Measurement

  • Four Differential LVPECL Outputs
  • Selectable Crystal or LVCMOS/LVTTL CLOCK Inputs
  • Up to 266 MHz Clock Operation
  • Output to Output Skew: 30 ps (Typ)
  • Device to Device Skew 200 ps (Max)
  • Propagation Delay 1.8 ns (Max)
  • Operating Range: VCC = 3.3 5% V( 3.135 to 3.465 V)
  • Additive Phase Jitter, RMS: 0.053 ps (Typ.)
  • Synchronous Clock Enable Control
  • Industrial Temp. Range (40C to 85C)
  • PbFree TSSOP20 Package
  • These are PbFree Devices
  • 10Gigibit Ethernet

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Type

Channels

Input / Output Ratio

Input Level

Output Level

VCC Typ (V)

tJitterRMS Typ (ps)

tskew(o-o) Max (ps)

tpd Typ (ns)

tR & tF Max (ps)

fmaxClock Typ (MHz)

fmaxData Typ (Mbps)

Reference Price

NB3N853531EDTR2G

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Active

CAD Model

Pb

A

H

P

TSSOP-20

1

260

REEL

2500

Y

Buffer

1

2:1:4

LVTTL

LVPECL

3.3

0.053

30

-

600

-

~NA~

Price N/A

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