Input Mux - 2:1, LVTTL / LVCMOS, 3.3 V, Fanout Buffer - 1:4 LVPECL

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Overview

The NB3N853501E is a low skew 3.3 V supply 2:1:4 clock distribution fanout buffer. An Input MUX selects one of two LVCMOS/LVTTL CLK lines by the CLK_SEL pin (HIGH for CLK1, LOW for CLK0) using LVCMOS/LVTTL levels. A CLK_EN pin can enable or disable the outputs synchronously to eliminate runt pulses using LVCMOS/LVTTL levels (HIGH to enable outputs, LOW to disable output).

  • Teleconmmunications
  • Networking
  • Computing Systems
  • SONET/SDH

  • LAN/WAN
  • Enterprise Servers
  • ATE
  • Test and Measurement

  • Four differential LVPECL Outputs
  • Two Selectable LVCMOS/LVTTL CLOCK Inputs
  • Up to 266 MHz Clock Operation
  • Output to Output Skew: 30 ps
  • Device to Device Skew 250 ps (Max.)
  • Propagation Delay 1.9 ns (Max.)
  • Operating range: VCC = 3.3 5% V( 3.135 to 3.465 V)
  • Additive Phase Jitter, RMS: 0.023 ps (Typ)
  • Industrial Temp. Range (40C to 85C)

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Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

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Type

Channels

Input / Output Ratio

Input Level

Output Level

VCC Typ (V)

tJitterRMS Typ (ps)

tskew(o-o) Max (ps)

tpd Typ (ns)

tR & tF Max (ps)

fmaxClock Typ (MHz)

fmaxData Typ (Mbps)

Reference Price

NB3N853501EDTR2G

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CAD Model

Pb

A

H

P

TSSOP-20

1

260

REEL

2500

Y

Buffer

1

2:1:4

LVTTL

LVPECL

3.3

0.062

30

-

700

266

~NA~

Price N/A

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