Drivers & Fanout Buffers | NB100LVEP17

Quad Differential Driver/Receiver/Buffer

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Overview

The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.

The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

Inputs of unused gates can be left open and will not affect the operation of the rest of the device.

  • 250 ps Typical Propagation Delay
  • Maximum Frequency >2.5 GHz Typical
  • Flow through Pinout
  • PECL Mode Operating Range: VCC = 2.375 V to 3.8 V, with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V, with VEE = -2.375 V to -3.8 V
  • Q Output will Default LOW with Inputs Open or at VEE
  • VBB Output

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NB100LVEP17DTR2G

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CAD Model

Pb

A

H

P

TSSOP-20

9.48

1

260

REEL

2500

Y

Signal Driver

4

1:1

LVDS

ECL

5

0.5

25

0.25

225

2500

2500

Price N/A

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Reliability Data

Die Related Summary Data

Device: NB100LVEP17DTR2G

Equivalent to wafer fab process: MOSAIC

Product Technology

Product Technology

Equivalent Device-Hours

MTBF/MTTF in Hours

FITS

MOSAIC

0

476668904

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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