2.5 V / 3.3 V 1:5 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer

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Overview

The MC100LVEP14 is a low skew 1 to 5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating under PECL conditions.

  • 100 ps Device-to-Device Skew
  • 25 ps Within Device Skew
  • 400 ps Typical Propagation Delay
  • Maximum Frequency > 2 GHz Typical
  • PECL and HSTL Mode: VCC = 2.375 V to 3.8 V with VEE = 0 V
  • NECL Mode: VCC = 0 V with VEE = -2.375 V to -3.8 V
  • LVDS Input Compatible
  • Open Input Default State

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Product

Status

CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

Type

Channels

Input / Output Ratio

Input Level

Output Level

VCC Typ (V)

tJitterRMS Typ (ps)

tskew(o-o) Max (ps)

tpd Typ (ns)

tR & tF Max (ps)

fmaxClock Typ (MHz)

fmaxData Typ (Mbps)

Reference Price

MC100LVEP14DTG

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CAD Model

Pb

A

H

P

TSSOP-20

1

260

TUBE

75

N

Buffer

1

2:1:5

CML

ECL

HSTL

LVDS

ECL

3.3

0.181

25

0.4

225

2000

-

Price N/A

More Details

MC100LVEP14DTR2G

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Active

CAD Model

Pb

A

H

P

TSSOP-20

1

260

REEL

2500

Y

Buffer

1

2:1:5

CML

ECL

HSTL

LVDS

ECL

3.3

0.181

25

0.4

225

2000

-

Price N/A

More Details

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