3.3V LVDS 1-Bit High Speed Differential Receiver

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Overview

This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock or data. The FIN1018 can be paired with its companion driver, the FIN1017, or with any other LVDS driver.

  • Media Tablets
  • Storage & Peripherals
  • Mobile Handsets
  • Wireless LAN Card & Broadband Access
  • PMP/MP3 Players
  • Greater than 400Mbs data rate
  • 3.3V power supply operation
  • 0.4ns maximum pulse skew
  • 2.5ns maximum propagation delay
  • Low power dissipation
  • Power-Off protection
  • Fail safe protection for open-circuit, shorted and terminated conditions
  • Meets or exceeds the TIA/EIA-644 LVDS standard
  • Flow-through pinout simplifies PCB layout
  • 8-Lead SOIC and US-8 packages save space

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Product

Status

CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

Type

Channels

Input / Output Ratio

Input Level

Output Level

VCC Typ (V)

tJitterRMS Typ (ps)

tskew(o-o) Max (ps)

tpd Typ (ns)

tR & tF Max (ps)

fmaxClock Typ (MHz)

fmaxData Typ (Mbps)

Reference Price

FIN1018K8X

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Obsolete

CAD Model

Pb

A

H

P

US8

1

260

REEL

3000

N

Signal Driver

1

1:1

LVDS

LVTTL

3.3

-

-

-

-

-

-

Price N/A

More Details

FIN1018MX

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Obsolete

CAD Model

Pb

A

H

P

SOIC-8

1

260

REEL

2500

N

Signal Driver

1

1:1

LVDS

LVTTL

3.3

-

-

-

-

-

-

Price N/A

More Details

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