3.3 V / 5.0 V ECL ÷·4 Divider

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Overview

The MC10/100EP33 is an integrated divide by 4 divider. The differential clock inputs.

The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, VBB should be left open.

The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EP33's in a system.

The 100 Series contains temperature compensation.

  • Phase Lock Loops
  • 320ps Propagation Delay
  • Maximum Frequency > 4 GHz Typical
  • PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Q Output will default LOW with inputs open or at VEE
  • VBB Output
  • Pb-Free Packages are Available

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Input Level

Output Level

VCC Typ (V)

fMax Typ (MHz)

tpd Typ (ns)

tR & tF Max (ps)

Reference Price

MC100EP33DG

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Active

CAD Model

Pb

A

H

P

SOIC-8

1

260

TUBE

98

Y

Divider

ECL

ECL

5

4000

0.38

200

Price N/A

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MC100EP33DTG

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Active

CAD Model

Pb

A

H

P

TSSOP-8

3

260

TUBE

100

Y

Divider

ECL

ECL

5

4000

0.38

200

Price N/A

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MC100EP33DTR2G

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Active

CAD Model

Pb

A

H

P

TSSOP-8

3

260

REEL

2500

Y

Divider

ECL

ECL

5

4000

0.38

200

Price N/A

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MC100EP33MNR4G

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Active

CAD Model

Pb

A

H

P

DFN-8

1

260

REEL

1000

Y

Divider

ECL

ECL

5

4000

0.38

200

Price N/A

More Details

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