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I2T100: 0.7 µm Process Technology

The Intelligent Interface Technology (I2T100) process from ON Semiconductor offers 100 V capability in a 0.7 µm CMOS mixed-signal technology. A variety of devices and process options provide a high degree of flexibility in combining mixed analog/digital with low-, medium- and high-voltage circuitry.


Features

  • 2-3 metal layers
  • Floating NMOS and PMOS transistors
  • Low threshold PMOS transistor
  • Medium- and high-voltage NDMOS transistors
  • Floating medium- and high-voltage NDMOS and PDMOS transistors
  • Low-, medium- and high-voltage bipolar transistors
  • Zener zap diode for OTP
  • Medium- and high-resistivity polysilicon resistors
  • Medium- and high-voltage floating capacitors
  • Deep N+ doped guard rings
  • Optional EEPROM
  • High temperature capability

Process Characteristics

Parameter Value
Operating Voltage 5.0 V
Substrate Material P-sub, twin-well
Drawn Transistor Length 0.7 µm
Gate Oxide Thickness 17.0/42.0 nm
Contact/Via Size 0.8 µm
Contacted Gate Pitch 2.8 µm
Top Metal Thickness 900 nm

Process Characteristics - Contacted Metal Pitch

Parameter Value
Metal 1 (contact/via) 2.8/2.6 µm
Metal 2 (via 1/via 2) 3.0/3.6 µm
Metal 3 (via 2) 4.0 µm
Metal Composition Al/Si/Cu
Isolation LOCOS
ILD Planarization BPSG
IMD Planarization PECVD/SOG

Sample Process Options

Parameter Mask Layers
2 metal, NSINKER, HIPO, CAPA, LowVt pMOS 22
3 metal, NSINKER, HIPO, CAPA, LowVt pMOS 24

Device Characteristics

(All Values Typical at 25°C)

Low-Voltage Transistors

NMOS Transistor Typical Value Unit PMOS Transistor Typical Value Unit Low Vt PMOS Transistor Typical Value Unit
Vt (20/0.7, linear extrapolated) 0.74 V Vt (20/0.7, linear extrapolated) -0.95 V Vt (20/0.7, linear extrapolated) -0.78 V
Vmax=Vbd 5.5 V Vmax=Vbd 5.5 V Vmax=Vbd 5.5 V
Ids (20/0.7, Vds=Vgs= 5 V) 358 µA/µm Ids (20/0.7, Vds=Vgs= 5 V) -176 µA/µm Ids (20/0.7, Vds=Vgs= 5 V) -121 µA/µm

Bipolar Transistors

NPN Floating @ 100 V Ae=5 µm² Area=3529 µm² Typical Value Unit NPN Floating @ 100 V Ae=49 µm² Area=4490 µm² Typical Value Unit
Hfe 60 - Hfe 40 -
Bvceo @ Ie=1 µA 25 V Bvceo @ Ie=1 µA 25 V
Bvces min 60 V Bvces min 60 V
Imax@142°C 0.3 mA Imax@142°C 2.7 mA
NPN Floating @ 60 V Ae= 5 µm² Area=1352 µm² Typical Value Unit NPN Floating @ 60 V Ae= 19 µm² Area=3081 µm² Typical Value Unit
Hfe 58 - Hfe 45 -
Bvceo @ Ie=1 µA 25 V Bvceo @ Ie=1 µA 25 V
Bvces min 60 V Bvces min 25 V
Imax@142°C 0.96 mA Imax@142°C 1.2 mA
Substrate PNP Ae= 460 µm² Area=2289 µm², collector grounded Typical Value Unit
Hfe 22 -
Bvceo @ Ie=1 µA 30 V
Vbe 0.57 V
PNP Floating @ 100 V Area=1542 µm² Typical Value Unit
Hfe 700 -
Bvceo @ Ie=1 µA 5.5 V
Bvces min 5.5 V
Imax@142°C 0.3 mA
PNP Area=5139 µm² Typical Value Unit PNP Area=98354 µm² Typical Value Unit
Hfe 800 - Hfe 880 -
Bvceo @ Ie=1 µA 25 V Bvceo @ Ie=1 µA 25 V
Bvces min 40 V Bvces min 80 V
Imax@142°C 0.3 mA Imax@142°C 0.3 mA

High-Voltage Transistors

Floating NMOS Transistor @ 100 V Typical Value Unit Floating PMOS Transistor @ 100 V Typical Value Unit
Vt (20/0.7, linear extrapolated) 0.74 V Vt (25/0.7, linear extrapolated) -1.1 V
Vmax=Vfloat to P-substrate 100 V Vmax=Vfloat to P-substrate 100 V
Vgsmax= Vbdmax 5.5 V Vgsmax= Vbdmax -5.5 V
Ids (20/0.7, Vd=Vg= 5 V) 358 µA/µm Ids (25/0.7, Vd=Vg= 5 V) -160 µA/µm
100 V NDMOS Typical Value Unit 30 V NDMOS (Thin Ox) Typical Value Unit 30 V NDMOS (Thick Ox) Typical Value Unit
Vt (W=40) 1 V Vt (W=40) 0.67 V Vt (W=40) 1.03 V
Vmax=Vbd 100 V Vmax=Vbd 30 V Vmax=Vbd 30 V
Vgsmax (full lifetime) 12 V Vgsmax (full lifetime) 5.5 V Vgsmax (full lifetime) 12 V
IDS (40/4, Vds=40 V, Vgs=4.0 V) 1210 µA IDS (40/4, Vds=20 V, Vgs=5.0 V) 4675 µA IDS (40/4, Vds=15 V, Vgs=4.0 V) 1450 µA/µm
Ron*W 74 kΩ*µm Ron*W 31.8 kΩ*µm Ron*W 22 kΩ*µm
Ron*Area 1532 mΩ*mm² Ron*Area 372 mΩ*mm² Ron*Area 257 mΩ*mm²
100 V Self-Aligned Floating NDMOS Typical Value Unit 60 V Self-Aligned Floating NDMOS Typical Value Unit 40 V Self-Aligned Floating NDMOS Typical Value Unit
Vt (W=40) 2.43 V Vt (W=40) 2.4 V Vt (W=40) 2.43 V
Vmax=Vbd 95 V Vmax=Vbd 60 V Vmax=Vbd 40 V
Vgsmax (full lifetime) 12 V Vgsmax (full lifetime) 12 V Vgsmax (full lifetime) 12 V
IDS (40/4, Vds=40 V, Vgs=4.0 V) 2050 µA/µm IDS (40/4, Vds=20 V, Vgs=5.0 V) 2250 µA/µm IDS (40/4, Vds=15 V, Vgs=4.0 V) 2200 µA/µm
Ron*W 33 kΩ*µm Ron*W 17.6 kΩ*µm Ron*W 11.6 kΩ*µm
Ron*Area 488 mΩ*mm² Ron*Area 153 mΩ*mm² Ron*Area 87 mΩ*mm²
90 V PDMOS Typical Value Unit 75 V PDMOS Typical Value Unit 40 V PDMOS Typical Value Unit
Vt (W=40) -1.13 V Vt (W=40) -1.13 V Vt (W=40) -1.13 V
Vmax=Vbd -100 V Vmax=Vbd -75 V Vmax=Vbd -40 V
Vgsmax (full lifetime) 12 V Vgsmax (full lifetime) 12 V Vgsmax (full lifetime) 12 V
IDS (40/4, Vds=40 V, Vgs=4.0 V) 980 µA/µm IDS (40/4, Vds=20 V, Vgs=5.0 V) 1125 µA/µm IDS (40/4, Vds=15 V, Vgs=4.0 V) 1175 µA/µm
Ron*W 77 kΩ*µm Ron*W 59 kΩ*µm Ron*W 45 kΩ*µm
Ron*Area 1050 mΩ*mm² Ron*Area 596 mΩ*mm² Ron*Area 380 mΩ*mm²
100 V Depleted PDMOS Typical Value Unit
Vmax=Vbd -100 V
|Vgsmax| (full lifetime) 5.5 V
IDS (40/3, Vds=-40 V, Vgs=0 V) 180 µA/µm
60 V Power-Kit NDMOS (optimized for switching applications) Typical Value Unit 40 V Power-Kit NDMOS (optimized for switching applications) Typical Value Unit
Vt (W=40) 2.45 V Vt (W=40) 2.45 V
Vmax=Vbd 60 V Vmax=Vbd 40 V
Vgsmax (full lifetime) 12 V Vgsmax (full lifetime) 12 V
IDS (40/4, Vds=40 V, Vgs=4.0 V) 2200 µA/µm IDS (40/4, Vds=20 V, Vgs=5.0 V) 2350 µA/µm
Ron*W 18 kΩ*µm Ron*W 11.3 kΩ*µm
Ron*Area 115 mΩ*mm² Ron*Area 65 mΩ*mm²

Diodes

Poly Diode Parameter, W=2.2 µm Typical Value Unit 90 V Floating HV Diode Area=6432 µm² Typical Value Unit Zener diode Smallest diode (3784 µm²) Typical Value Unit
BV 6.76 V BV 90 V BV 9.5 V
Imax (2.2 µm) ~300 µA Isub/Ia (Ia=2.4 mA) ~2 % Ron in Vbd mode 1560 Ω
Ileak (2.2 µm) @-5 V ~90 µA

Capacitors (Parameter @ 25°C)

Poly/Thin GateOx/N++ [CAPA] Typical Value Unit Poly/Poly (medium voltage floating) Typical Value Unit Metal1/Poly/Metal2 (high voltage floating) Typical Value Unit
Cplate 0.75 fF/µm² Cplate 0.36 fF/µm² Cplate 0.075 fF/µm²
Vbd_max (full lifetime) 15 V Vbd_max (full lifetime) 30 V Vbd_max (full lifetime) 100 V

Resistors

Resistor Type Typical Value Unit
High-Resistance Poly [HIPO] 1825 Ω/square
Medium-Resistance Poly [MOPO] 190 Ω/square
Low-Resistance Poly [LOPO] 27 Ω/square
N-Well 1000 Ω/square
Pbody Diffusion in Ntub 1250 Ω/square
N+ Diffusion in P-well 67.5 Ω/square
P+ Diffusion in N-well 96 Ω/square

Libraries

Digital Design - Standard Cell Core Library
Synopsys Design Compiler
pn sum: 5.7 µm
Area of 2-input nand (na21): 207 µm²
Gate density (na21 @ 100% utilization): 4.831 k gates/mm²
Scan Flop density (scan flops @ 100% utilization): 0.5574 k ff/mm²
Average power (@ 5.0 V): 2.32 µW/MHz/gate

CAD Tool Compatibility

Digital Design
Synopsys Design Compiler
Cadence Verilog
Analog Design
Cadence DFII (4.4.6)
Spectre
Place and Route
Synopsys Apollo
Cadence Silicon Ensemble
Physical Verification
Mentor Calibre

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