P-Channel Logic Level Enhancement Mode Field Effect Transistor -30V, -30A, 42mΩ

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Overview

These P-Channel logic level enhancement mode power field effect transistors are produced using ON Semiconductor's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as DC/DC converters and high efficiency switching circuits where fast switching, low in-line power loss, and resistance to transients are needed.

  • This product is general usage and suitable for many different applications.
  • -30 A, -30 V
    RDS(ON) = 0.042 Ω @ VGS= -4.5 V
    RDS(ON) = 0.025 Ω @ VGS= -10 V
  • Critical DC electrical parameters specified at elevated temperature
  • Rugged internal source-drain diode can eliminate the need for an external Zener diode transient suppressor
  • High density cell design for extremely low RDS(ON)
  • 175°C maximum junction temperature rating

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Status

CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

V(BR)DSS Min (V)

RDS(on) Max @ VGS = 10 V (mΩ)

Channel Polarity

Configuration

VGS Max (V)

VGS(th) Max (V)

ID Max (A)

PD Max (W)

RDS(on) Max @ VGS = 2.5 V (mΩ)

RDS(on) Max @ VGS = 4.5 V (mΩ)

Qg Typ @ VGS = 4.5 V (nC)

Qg Typ @ VGS = 10 V (nC)

Ciss Typ (pF)

Reference Price

NDB6030PL

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Obsolete

CAD Model

Pb

A

H

P

D2PAK-3 / TO-263-2

1

260

REEL

800

N

-30

25

P-Channel

Single

16

-3

-30

75

-

42

-

26

1570

Price N/A

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