Asymmetric Dual N-Channel PowerTrench® Power Stage MOSFET, 25V

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Overview

This device includes two specialized N-Channel MOSFETs in a dual PQFN package. The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronousSyncFET (Q2) have been designed to provide optimal power efficiency.

  • Distribution
  • Notebook PC
  • Q1: N-Channel
    Max rDS(on) = 5.0 mΩ at VGS = 10 V, ID = 17.5 Al
    Max rDS(on) = 5.7 mΩ at VGS = 4.5 V, ID = 16 Al
  • Q2: N-Channel
    Max rDS(on) = 1.8 mΩ at VGS = 10 V, ID = 30 Al
    Max rDS(on) = 2.2 mΩ at VGS = 4.5 V, ID = 27 Al
  • Low inductance packaging shortens rise/fall times, resulting in lower switching lossesl
  • MOSFET integration enables optimum layout for lower circuit inductance and reduced switch node ringingl
  • RoHS Compliantl

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Product

Status

CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

Channel Polarity

Silicon Family

Package Name

Type

Gate Level

Wide SOA Mosfets

Configuration

OPN in older Technology

V(BR)DSS Min (V)

RDS(on) Max @ VGS = 10 V (mΩ)

Vgs (V)

Vgs(th) Max (V)

ID Max (A)

PD Max (W)

RDS(on) Max @ VGS = 2.5 V (mΩ)

RDS(on) Max @ VGS = 4.5 V (mΩ)

Qg Typ @ VGS = 4.5 V (nC)

Qg Typ @ VGS = 10 V (nC)

Ciss Typ (pF)

Qgd Typ @ VGS = 4.5 V (nC)

Qrr Typ (nC)

Coss Typ (pF)

Crss Typ (pF)

Reference Price

FDMS3624S

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Obsolete

CAD Model

Pb

A

H

P

PQFN-8

1

260

REEL

3000

N

N-Channel

PowerTrench® T1

Power 56 (SO-8FL)

Low-Medium Voltage

Logic

0

Dual

0

25

Q1: 5.0, Q2: 1.8

12

Q1: 2.0, Q2: 2.2

Q1: 17.5, Q2: 30.0

Q1:2.2, Q2: 2.5

-

Q1: 5.7, Q2: 2.2

30

27

4045

-

-

-

-

Price N/A

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