Dual P-Channel Digital FET -25V, 0.41A, 1.1Ω

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Overview

These dual P-Channel logic level enhancement mode field effect transistors are produced using a proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS.

  • This product is general usage and suitable for many different applications.
  • -25 V, -0.41 A continuous, -1.5 A Peak.
  • RDS(ON) = 1.1 Ω @ VGS= -4.5 V,
  • RDS(ON) = 1.5 Ω @ VGS= -2.7 V.
  • Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) <1.5 V).
  • Gate-Source Zener for ESD ruggedness (>6kV Human Body Model).
  • Compact industry standard SC70-6 surface mount package.

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Product

Status

CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

V(BR)DSS Min (V)

RDS(on) Max @ VGS = 10 V (mΩ)

Channel Polarity

Configuration

VGS Max (V)

VGS(th) Max (V)

ID Max (A)

PD Max (W)

RDS(on) Max @ VGS = 2.5 V (mΩ)

RDS(on) Max @ VGS = 4.5 V (mΩ)

Qg Typ @ VGS = 4.5 V (nC)

Qg Typ @ VGS = 10 V (nC)

Ciss Typ (pF)

Reference Price

FDG6304P

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Active

CAD Model

Pb

A

H

P

SC-88-6 / SC-70-6 / SOT-363-6

1

260

REEL

3000

Y

-25

-

P-Channel

Dual

-8

-1.5

-0.41

0.3

Q1=Q2=1800

Q1=Q2=1100

1.8

1.1

62

$0.1655

More Details

FDG6304P-F169

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Obsolete

CAD Model

Pb

A

H

P

SC-88-6 / SC-70-6 / SOT-363-6

1

260

REEL

3000

N

-25

-

P-Channel

Dual

-8

-8

-0.41

0.3

1500

1100

-

-

62

Price N/A

More Details

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