What physical DIO pins are used for programming on RSL10 SoC?

Hi all, what physical DIO pins are used for programming? I am building a custom board and am having trouble figuring out from the datasheet which pins to use. I come from a background with Nordic nRF series chips and it’s very easy to understand - 4 routes, VDD GND SWDIO SWDCLK. It appears to program a board with JLink, this RSL10 needs 5 connections? JTag IN, JTag OUT, then a clock signal, VDD and GND.

I can see that DIO[14] and [15] are JTag in and out, and you can source VDD/GND from anywhere, but what pin supplies clock signal for programming? And why are there 2 DIO pins for JTag, why not one line for IO?


Hi noah,

The RSL10 supports 3 options when it comes to debug interface:

  • 2-wire SWD - Always available via the dedicated SWDIO and SWCLK pads.
  • 4-wire JTAG - Additionally requires DIO14 and DIO15.
  • 5-wire JTAG - Additionally requires DIO14, DIO15 and DIO13.

All of the available evaluation boards use SWD by default.
You can look at schematics of the evaluation boards to get an idea how to wire the SWD:

  • RSL10 Evaluation Board - By default uses SWD with standard 10-pin Cortex connector. Can be modified to JTAG by soldering additional resistors.
  • RSL10-SENSE-GEVB - Uses SWD with standard 10-pin Cortex connector and 10-pin needle connector.
  • RSL10-COIN-GEVB - Uses SWD with 6-pin needle connector.

Best regards,

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Hi, what DIO[n] numbers are required for the 4-wire JTAG connection? I need DIO14, DIO15, and then what DIO numbers?

I think you can refer to RSL10 Evaluation board datasheet (EVBUM2529/D) page 12. It shows that JTAG TMS and JTAG TCK are connected to dedicated pins, while TDO and TDI go to DIO14 and DIO15 on the RSL10 chip.




Please refer to our post on programming options on debug interface of RSL10 :

What physical DIO pins are used for programming on RSL10 SoC? - #4 by lukas.mandak

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I’m glad this thread exists, because I am also trying to figure this out — the RSL10 datasheet, NCV-RSL10 datasheet, the RSL10 hardware reference guide, etc make no mention whatsoever of SWD.… and yet so many reference design schematics use SWD! It was making me very nervous about how to program the chip!

Where is the documentation on SWD and JTAG for the RSL10?
What configuration steps are required to enable one mode or another?

I’m trying to create a design such that the RSL10 chip’s firmware can be reprogrammed by another MCU on the same board; is SWD or JTAG a better option, or is it best just to use the bootloader’s UART pins?
If the bootloader does not come factory-installed (talking about the bare IC, not evaluation boards), I presume UART programming is not a good choice.


  • If the chip does not have bootloader, it has to use JTAG or SWD to load the code.

  • If the chip already has bootloader, you can use UART to reprogram by another MCU therefore you don’t need JTAG anymore.
    In addition you can use our FOTA method to reprogram the memory .

The RSL10 software ecosystem includes a set of tools that allows Firmware Over-The-Air (FOTA) updates from a PC with the RSL10 USB dongle to a remote RSL10 device over a Bluetooth Low Energy wireless link. On the PC side, a Python utility (mkfotaimg.py) generates FOTA-compatible firmware images and a PC command line tool (FOTA.Console.exe) transfers the images to the remote device. The PC command line tool uses the RSL10 USB Dongle as a central device to scan, connect and transmit the firmware image. The remote RSL10 device firmware side consists of a bootloader program, sample code, and a FOTA Bluetooth Low Energy stack that contains the Device Firmware Update (DFU) Bluetooth Low Energy component. Figure 1, below, illustrates a typical FOTA update setup from the PC point of view:


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That FOTA utility looks really handy!

The bootloader guide (document number M-20851-004) implies the bootloader does not come pre-loaded, so for first-time programming I might be stuck emulating a SWD programmer on the other MCU… The dream scenario would be to use bluetooth right on the production line, brand-new out of the box.

Your screenshot of the debugger dialog makes it pretty clear that both SWD and JTAG are supported, and schematics for various development boards can be referenced for what pins are used, so that’s good. Without an actual document that mentioned SWD, that was not a safe assumption for me to make.

I suppose I’d better talk to a salesperson to find out if bootloader-preprogrammed RSL10 chips are available for purchase.


JTAG and SWD are the only ways to program the device upon receipt of new goods. Once you load the FOTA stub, you can use it at that point, but we do not offer any variants which have this pre-loaded.
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The RSL10 Hardware Reference calls the debug port SWJ-DP to signify that is is a combined SWD and JTAG debug port.
You can find more details about the debug port and how to configure it for either protocol in section 3.2 Debug Port of the RSL10 Hardware Reference.

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