I’m trying to add FOTA functionality to a fork of the peripherial_server_uart code. Currently, the project is generating the .fota file (I haven’t actually tested FOTA functionality yet.), but now when I go running the firmware normally in Eclipse it’s as if nothing gets flashed to the device. It just continues running the previous application.
After building all of the expected binaries are present and have a current timestamp.
01/18/2022 01:12 PM 23,724 peripheral_server_uart.bin
01/18/2022 01:12 PM 310,476 peripheral_server_uart.elf
01/18/2022 01:12 PM 0 peripheral_server_uart.fota
01/18/2022 01:12 PM 66,804 peripheral_server_uart.hex
01/18/2022 01:12 PM 190,186 peripheral_server_uart.map
During a clean build I see an assertion about invalid image start address, which is triggered by the FOTA post-build script.
Invoike FOTA Build Scripts
arm-none-eabi-objcopy -O binary "peripheral_server_uart.elf" "peripheral_server_uart.bin" && "C:/Users/steven/Projects/BioPause/Firmware/peripheral_server_uart/RTE/Device/RSL10/mkfotaimg.py" -o "peripheral_server_uart.fota" "C:/Users/steven/Projects/BioPause/Firmware/peripheral_server_uart/RTE/Device/RSL10/fota.bin" "peripheral_server_uart.bin"
AssertionError: Wrong image start address (0x00129800/0x00129000)
make[1]: [makefile:71: post-build] Error 1 (ignored)
Invoking: Cross ARM GNU Create Flash Image
arm-none-eabi-objcopy -O ihex "peripheral_server_uart.elf" "peripheral_server_uart.hex"
Finished building: peripheral_server_uart.hex
Invoking: Cross ARM GNU Print Size
arm-none-eabi-size --format=berkeley "peripheral_server_uart.elf"
text data bss dec hex filename
23624 100 10160 33884 845c peripheral_server_uart.elf
Finished building: peripheral_server_uart.siz
Incremental builds seem to go without errors
13:15:38 **** Incremental Build of configuration Debug for project peripheral_server_uart ****
make all
Invoking: Cross ARM GNU Print Size
arm-none-eabi-size --format=berkeley "peripheral_server_uart.elf"
text data bss dec hex filename
23624 100 10160 33884 845c peripheral_server_uart.elf
Finished building: peripheral_server_uart.siz
GDB J-Link output
SEGGER J-Link GDB Server V6.96 Command Line Version
JLinkARM.dll V6.96 (DLL compiled Feb 19 2021 09:55:51)
Command line: -if swd -device RSL10 -endian little -speed 1000 -port 2331 -swoport 2332 -telnetport 2333 -vd -ir -localhostonly 1 -singlerun -strict -timeout 0 -nogui
-----GDB Server start settings-----
GDBInit file: none
GDB Server Listening port: 2331
SWO raw output listening port: 2332
Terminal I/O port: 2333
Accept remote connection: localhost only
Generate logfile: off
Verify download: on
Init regs on start: on
Silent mode: off
Single run mode: on
Target connection timeout: 0 ms
------J-Link related settings------
J-Link Host interface: USB
J-Link script: none
J-Link settings file: none
------Target related settings------
Target device: RSL10
Target interface: SWD
Target interface speed: 1000kHz
Target endian: little
Connecting to J-Link...
J-Link is connected.
Firmware: J-Link ARM V8 compiled Nov 28 2014 13:44:46
Hardware: V8.00
S/N: 268006065
OEM: SEGGER-EDU
Feature(s): FlashBP, GDB
Checking target voltage...
Target voltage: 1.83 V
Listening on TCP/IP port 2331
Connecting to target...
Connected to target
Waiting for GDB connection...Connected to 127.0.0.1
Reading all registers
Read 4 bytes @ address 0x00000000 (Data = 0x20002000)
Read 2 bytes @ address 0x00000000 (Data = 0x2000)
Received monitor command: speed 1000
Target interface speed set to 1000 kHz
Received monitor command: clrbp
Received monitor command: reset
Resetting target
Received monitor command: halt
Halting target CPU...
...Target halted (PC = 0x00100158)
Received monitor command: regs
R0 = 00100159, R1 = 00000007, R2 = 20006000, R3 = E000ED00
R4 = 00100000, R5 = 00000007, R6 = FFFFFFFF, R7 = 40000E2C
R8 = 4200A700, R9 = 00081A00, R10= CDAF6F43, R11= 255DFB5F
R12= 00000001, R13= 20005FFC, MSP= 20005FFC, PSP= 3FAD55AC
R14(LR) = 000002E5, R15(PC) = 00100158
XPSR 61000000, APSR 60000000, EPSR 01000000, IPSR 00000000
CFBP 00000001, CONTROL 00, FAULTMASK 00, BASEPRI 00, PRIMASK 01
Security extension regs:
MSP_S = 00000000, MSPLIM_S = 00000000
PSP_S = 00000000, PSPLIM_S = 00000000
MSP_NS = 20005FFC, MSPLIM_NS = 00000000
PSP_NS = 3FAD55AC, PSPLIM_NS = 00000000
CONTROL_S 00, FAULTMASK_S 00, BASEPRI_S 00, PRIMASK_S 00
CONTROL_NS 00, FAULTMASK_NS 00, BASEPRI_NS 00, PRIMASK_NS 01
Reading all registers
Received monitor command: speed auto
Select auto target interface speed (2000 kHz)
Received monitor command: flash breakpoints 1
Flash breakpoints enabled
Received monitor command: semihosting enable
Semi-hosting enabled (Handle on BKPT)
Received monitor command: semihosting IOClient 1
Semihosting I/O set to TELNET Client
Received monitor command: SWO DisableTarget 0xFFFFFFFF
SWO disabled successfully.
Received monitor command: SWO EnableTarget 0 0 0x1 0
SWO enabled successfully.
Downloading 16016 bytes @ address 0x00129800 - Verified OK
Downloading 7384 bytes @ address 0x0012D690 - Verified OK
Downloading 216 bytes @ address 0x0012F368 - Verified OK
Downloading 8 bytes @ address 0x0012F440 - Verified OK
Downloading 100 bytes @ address 0x0012F448 - Verified OK
Comparing flash [....................] Done.
Writing register (PC = 0x 129958)
Read 4 bytes @ address 0x00129958 (Data = 0x47804802)
Read 2 bytes @ address 0x00129958 (Data = 0x4802)
Received monitor command: clrbp
Received monitor command: reset
Resetting target
Received monitor command: halt
Halting target CPU...
...Target halted (PC = 0x00100158)
Received monitor command: regs
R0 = 00100159, R1 = 00000007, R2 = 20006000, R3 = E000ED00
R4 = 00100000, R5 = 00000007, R6 = FFFFFFFF, R7 = 40000E2C
R8 = 4200A700, R9 = 00081A00, R10= CDAF6F43, R11= 255DFB5F
R12= 00000001, R13= 20005FFC, MSP= 20005FFC, PSP= 3FAD55AC
R14(LR) = 000002E5, R15(PC) = 00100158
XPSR 61000000, APSR 60000000, EPSR 01000000, IPSR 00000000
CFBP 00000001, CONTROL 00, FAULTMASK 00, BASEPRI 00, PRIMASK 01
Security extension regs:
MSP_S = 00000000, MSPLIM_S = 00000000
PSP_S = 00000000, PSPLIM_S = 00000000
MSP_NS = 20005FFC, MSPLIM_NS = 00000000
PSP_NS = 3FAD55AC, PSPLIM_NS = 00000000
CONTROL_S 00, FAULTMASK_S 00, BASEPRI_S 00, PRIMASK_S 00
CONTROL_NS 00, FAULTMASK_NS 00, BASEPRI_NS 00, PRIMASK_NS 01
Reading all registers
Starting target CPU...
