# RSL10 ADC - measuring voltage divider

## Question: I’m measuring the the output of a voltage divider using the RSL10 ADC and i notice that the output of the voltage divider is not correct when connected to the ADC input. For example I have the following Voltage divider: VCC = 2.5V

``````     |
R1=499K
|
--- Vout
|
R2=499K
|
``````

`````` GND
``````

In this case Vout should be 1.250V but when i connect to the ADC, I noticed that Vout goes around 1.67V (like there i an additional pull up resistor of 499K parallels to R1 - i verified and the pullup of the channel is disabled).
I also noticed that if i change the sampling frequency the output of the voltage divider (Vout) slightly change. If i lower the value of R1 and R2 to 1K then i get the more right output. I think this is relate to the input characteristic of the ADC channel but i cannot find any documentation about it.
In addition, if I buffer the output of the voltage diver using an Opamp, then i read the correct value. Any suggestions/explanation?
BTW, an other strange thing is that if I remove R1 and R2=499K then Vout is not 0V but around 1.5-1.6V.

Hope somebody can help exampling the input characteristic of the analog channel or why i experience this issues…

1 Like

Hi Nicola, I am happy to help answer your questions. This sounds like a slew rate issue with the internal ADC MUX.

The ADC uses an internal MUX to constantly switch between a number of different sources, and when the ADC switches sources it takes time to settle from one value to the next. The rate of change (slew rate) is dependent on the capacitance of the internal ADC signal trace, and the current charging/discharging it.
In your case, It is likely the ADC was reading a value higher then Vout(such as 1.8V), and the high value for R2 is limiting the discharge current, and increasing the time needed to settle. Using lower resistor values will decrease the amount of time it takes to settle between values. Changing the sampling frequency will change the amount of time available to settle between values, so in order to sample at high frequencies we need to have a very fast slew rate.

Using a high impedance op-amp to buffer your signal is actually one of the ideal solutions to this problem. The op-amp will sink/source the necessary amount of current to adjust the ADC pin quickly, without impacting Vout.

If you remove R1 and R2 then you are leaving the input pin in a “floating” state, which is not the same as 0V. To read 0V you must actually connect the ADC to 0V, directly or with a resistor.

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Thank you for the explanation, make sense.
How much is the internal ADC mux capacitance?

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@nicola

Would you please refer to our community forum thread regarding ADC measurements at:

Thank you for using our community forum!

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