RadioLab and AXM0F243

Hello,

Question in RadioLab in configuring the Physical layer using the AXM0F243. My carrier is 169.7Mhz using a Fxtal at 16Mhz. Would like to increase datarate (Bitrate(wire) [Kbits/s]) to 100Kbps but can only go up to 25Kbps. What are the parameters to get to 100kbps.

Thank you

Hi Jon, what kind of limitation are you seeing? I am using RadioLab V2.8e and can generate a project running at 100kbps with a 16MHz XTAL.

For more info on how to setup the GUI, take a look at the guide under Help/Documentation/ :
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Thanks!

Hello Georgi,

I’m using a TCXO on pin 39,40 not a Xtal everything else is the same. I did try a XTAL on these pins and it did not work with my TCXO. I’m using the TYKTBLSANF-16.000000 part for the TCXO

Datasheet

Hi Jon. To better understand: are you seeing the problem in generating the project in RadioLab (the data rate field not allowing you to set more than 25 kbps) or during execution of the program (the PLL doesn`t lock)?

Since you are using a TCXO different from the one we use in our reference design (NT2016SA), you should be careful in designing the correct driving circuitry. Here an app note on the topic https://www.onsemi.cn/pub/Collateral/AND9317-D.PDF

Hey Georgi,
Thanks for the reply - so let me tell you what I am observing:
All Configs have Master in TX periodic at 1.46 secs and Slave at continuous RX with ACK
At 60 bps everything works - REF OSC can be either TCXO or XTAL HOWEVER Loop Filter must be INTERNAL nothing works with Loop Filter EXTERNAL. AFC is at 1Khz
OUTPUT of MASTER:
ST:0x03 ERR:0x00
ST:0x04 ERR:0x02
ST:0x00 ERR:0z00
ST:0z04 ERR:0x00
Happy face
At 70bps the communication link is intermittent whether TCXO or XTAL or AFC is 1Khz or 10Khz
Output when working is same as above.
Output when not working is as follows:
ST:0x03 ERR:0x00
ST:0x04 ERR:0x02
ST:0x04 ERR:0x03
I have not gone higher than 70bps

Hi Jon, please review the AX-RadioLAB_AX5043_user_manual.pdf as suggested in the previous message and check if your settings are being chosen correctly.
Referring to what you wrote for example:

  • when changing “Ref Osc” from TCXO to XTAL, the internal load capacitor bank on CLK_N and CLK_P is connected thus perturbing the TCXO operation.

  • The “Loop Filter Config” sets bits in the PLLLOOP register thus selecting an internal or external (between L1/L2, pins 10/11). If no external inductor is present, the PLL will never lock when set to external.

Georgi,

The problem could be my loop filter. So my external inductor is 68nH. My loop filter (pin 9) is 39pf in parallel with a resistor (12.1K) and Cap (10nf) in series. With a trace between the cap and resistor (that are in series) going back to pin 37. My question: Are these the optimum values for approx 170Mhz carrier?

Hi Jon, since you are focusing on 170 MHz, my suggestion would be to copy the schematic and layout of our ADDON module for 169MHz https://www.onsemi.com/pub/Collateral/ADD5043-169-2-GEVK%20SCHEMATIC.PDF .

In general, the inductor values suggested on Table 9 of the AX5043 Datasheet , are a good starting point, but for finding an optimal value, you are required to test directly on your design. This because the actual value varies a lot from PCB to PCB (layout/stack-wise), but also from inductor to inductor (brand-wise).