KB: Suggested Settings and Register Definitions for the RSL10 Output Driver (OD)

[RSL10 - Knowledge Base]


The RSL10 hardware includes an Output Driver that is capable of mono digital audio play-back over a positive and negative pair of its DIO pins.

Given that OD has a number of register configurations that influence the audio quality received over the output pins, what recommendations and guidelines does ON Semiconductor offer to allow users to get started with selecting the appropriate settings?


Suggested OD Register Values

This register controls the high-pass filter that can help to remove noise artifacts, which can occur in situations where the level of the output signal is very low and there is a DC offset present in the signal.

β€˜AUDIO_OD_CFG->DCRM’ is recommended to be set at 20Hz (0x08 @ 1MHz OD_CLK, 0x06 @ 2MHz OD_CLK).

This register can be used to enable or disable dithering of the output data stream. Use of dithering is recommended, as this avoids idle tones and other artifacts produced by sigma-delta modulation.

β€˜AUDIO_OD_CF->DITHER’ is recommended to be set to Enabled (0x01).

Clock Edge
This register controls whether the output driver updates the output on the rising
or the falling edge of the output driver’s clock.

β€˜AUDIO_OD_CFG->CLK_EDGE’ is recommended to be set to Falling Edge (0x00).

This register controls internal configuration of the sigma-delta modulator.

β€˜AUDIO_SDM_CFG->SDM_CONFIG’ is recommended to be set as β€˜0x0005d012’, although tweaking this value slightly can have a significant impact on the audio quality, depending on the use case.

DIO Pin Selection

The OD outputs should be sent to 2-3 separate DIOs each if the receiver impedance is low, as described in the RSL10 Hardware Reference Manual. This is required because the low impedance receiver will require several DIOs connected in parallel to supply the necessary current.

The OD output can be driven by one or multiple pairs of DIO pads by configuring the DIO_CFG[15:0] registers to DIO_MODE_OD_P and DIO_MODE_OD_N.

Note: Connecting multiple DIO pads in parallel can degrade the audio quality, especially at higher VDDO voltages, due to timing differences. Therefore, pairing multiples of following DIO groups is recommended:
β€’ OD_P: DIO5, DIO6, DIO7, DIO10
β€’ OD_N: DIO0, DIO1, DIO2, DIO3

OD 1kHz Sine Wave Evaluation

The following RSL10 project can be used to build firmware intended to assist in the debugging and configuration of the Output Driver. The firmware will send a continuous 1kHz Sine Wave (sampled @ 16kHz) over the OD output pins (Positive - DIO0 ; Negative - DIO1) and can be used optimize the register configurations to achieve the optimal audio playback quality.

OD_SINE_TEST.zip (57.2 KB)

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