[RSL10 - Knowledge Base]
One of the most compelling factors to design with the RSL10 device is it’s ultra low-power consumption when operating in the Sleep mode. What are the other operating modes available on the device, what are the general use-cases, and which subsystems are connected/powered-on/available in each mode?
Run mode is the default operating setup for the RSL10 device. In this mode, all of the device’s subsystems are connected and provided with power. Many of the subsystems can be enabled/disabled by writing to the appropriate device registers, but everything else is accessible and maintained.
This mode is utilized during the execution of the device’s tasks, while the operations are shifted into the Standby/Sleep modes, discussed below, to save on power consumption when the device is able to sit idle.
Standby mode is often used to reduce the average power consumption of the device when not all internal systems can be powered down or disconnected, or when you require all of the memory instances to be retained.
In this operating mode, the clock to the logic and memory is no longer running, and both sub-systems are on reduced power to lower the overall consumption. All of the dynamic memory regions retain their data in this mode because they are not fully disconnected from their power supply.
The Analog Control System, bandgap, DC-DC converter, charge pump and digital regulator are all kept active in this mode, but the RF block can be disconnected from power through the ACS_VDDRF_CTRL register.
Sleep Mode enables the operating conditions that demonstrates the RSL10’s ultra low-power consumption by disconnecting all of the sub-systems possible when the device is not required to execute any code.
When operating in this mode, the only system that has to retain its settings is the Analog Control System and the only system that has to retain power is the wakeup logic. The bandgap, regulators, RF block and other systems are all disconnected from power entirely and need to be reconfigured upon device wakeup.
Optionally, the digital core and memory regions can be kept connected in a low-power mode, but this does lead to a slightly increased power consumption while sleeping.
By allowing the digital block to operate in this low power mode, it is possible to retain the DIO Pad configurations by setting the PADS_RETENTION_EN bit in the ACS_WAKEUP_CTRL register, which will restore all of the DIO Pads to the previous operating condition during the execution of the boot PROM code after waking-up.
By allowing the memory regions to operate in this low power mode, it is also possible to retain certain parts of dynamic memory which may have important run-time information saved. This is demonstrated in the ‘peripheral_server_sleep’ application, in which the BLE Stack state & configurations are written to and restored from DRAM memory on every sleep cycle, so that the BLE Connection can be maintained.