KB: How to trim the RSL10 crystal

Question

The PLL_CTRL_XTAL_TRIM register is usually used to adjust the frequency of the crystal, but sometimes we have found this doesn’t work. How can we solve this problem?

Recommendation

Check your crystal datasheet. RSL10 needs 8pF. (The trim range is from 6pF to 10pF for the internal cap). If the crystal can’t meet the requirement, you need to add an external cap for it, or change to using a suitable crystal.

We are assessing the suitability of a new 48 MHz crystal part for operation with the RSL10. I can’t find any helpful guidance as to how to utilise the trimming capability of the RSL10 in order to help with this procedure. Is there some form of white paper / hardware designer’s guide document that goes into some detail around the crystal setup ?

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Please see above picture, you can use it for the 48Mhz crystal trim.
It use one byte value for trimming, 5MSB and 3LSB included. In the usage, 5MSB should be for the Rough adjustment 3MSB should be for the accurate adjustment. You can test it and verify it in the equipment. to get a suitable value for your crystal

The RSL10 Hardware Ref, chapter 8.2.1 states the following:
“If the XTAL_CTRL_BYPASS bit in the XTAL_CTRL register is cleared, the crystal is automatically trimmed to 48
MHz using an iterative algorithm, with the trimming rate configured using the XTAL_CTRL_XTAL_CKDIV bit-field
(larger divisors provide longer clock trimming periods for more averaging). If the XTAL_CTRL_BYPASS bit in the
XTAL_CTRL register is set, the value set to the PLL_CTRL_XTAL_TRIM bit-field is used directly.”

So do I also need to set the the XTAL_CTRL_BYPASS bit in order to utilise the value set into PLL_CTRL_XTAL_TRIM ?

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if you just modify the trim byte. can you get the value you want in the test equipment side?